參數(shù)資料
型號(hào)： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁(yè)數(shù)： 38/99頁(yè)
文件大?。?/td> 663K
代理商： TVP3025-175
2–24
Table 2–8. Multiplex Mode and Bus-Width Selection (Continued)
MODE
SUB-
MODE
MULTIPLEX-
CONTROL
REGISTER 1
(HEX)
MULTIPLEX-
CONTROL
REGISTER 2
(HEX)
DATA
BITS
PER
PIXEL
(see
Note 8)
PIXEL
BUS
WIDTH
MULTI-
PLEX
RATIO
(see
Note 9)
OVERLAY
BITS
PER
PIXEL
TABLE
REFERENCE
(see
Note 10)
True-
Color
1
4E
03
24
32
1
NA
d1
4E
04
24
64
2
NA
d2
24-bit
4F
03
24
32
1
NA
d3
4F
04
24
64
2
NA
d4
2
4D
02
16
16
1
NA
d5
(5–6–5)
XGA
4D
03
16
32
2
NA
d6
4D
04
16
64
4
NA
d7
3
4C
02
15
16
1
NA
d8
(5–5–5)
TARGA
4C
03
15
32
2
NA
d9
4C
04
15
64
4
NA
d10
4
4B
02
16
16
1
NA
d11
16-bit
(6–6–4)
4B
03
16
32
2
NA
d12
4B
04
16
64
4
NA
d13
5
49
02
12
16
1
NA
d14
12-bit
(4–4–4)
49
03
12
32
2
NA
d15
49
04
12
64
4
NA
d16
NOTES:
8. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,
often referred to as the number of bit planes.
9. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists
of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK.
Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK
divide ratio is not automatically set by mode selection but must be programmed in the output-clock-
selection register by the user.
10. This column is a reference to Tables 2–9 through 2–11, where the actual manipulation of pixel information
and pixel latching sequences are illustrated for each of the multiplexing modes.
11. It is recommended that all unused input terminals be connected to ground to conserve power.
12. Auxiliary control register bit 0 and color-key-control register bit 4 default to palette graphics at reset. If direct
color operation is desired, then these bits must be set to logic 0.
13. Multiplex-control register 1 bit 3 must be set to logic 1 for direct or true-color mode operation. This bit setting
is different than the TVP3020 VIP.
14. If the device is reset to the BT485 mode, to program the multiplexer for the TVP3020 true-color modes,
true-color control register bit 2 must be set to a logic 0. This is automatically the case if the device is reset
into the TVP3020 mode.
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
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