參數(shù)資料
型號(hào)： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁(yè)數(shù)： 23/99頁(yè)
文件大?。?/td> 663K
代理商： TVP3025-175
2–9
The PLLs are programmed through a group of four registers on the TVP3025 indirect register map. The
registers are listed in the following table.
INDEX
REGISTER
002C
PLL control register
002D
Pixel clock PLL data register
002E
MCLK PLL data register
002F
Loop clock PLL data register
Programming of the M, N, and P value registers is accomplished by writing the appropriate values to bits
0 and 1 of the PLL control register (002C) according to the following table.
BIT 1
BIT 0
REGISTER
0
0
N value register (7-bit)
0
1
M value register(7-bit)
1
0
P value register(post scalar, 2-bit)
1
1
Status register(read-only)
The PLL control register pointer bits above (one set for each PLL data register) are independently
auto-incremented following a write cycle to the corresponding PLL data register. Whenever bits 1 and 0 are
both written with zeros, all three sets of pointer bits are reset to zero. The current status of each pointer can
be identified by reading the PLL control register (002C) according to the following table.
PLL CONTROL
REGISTER BITS
POINTER
1:0
Pixel clock PLL data register pointer
3:2
MCLK PLL data register pointer
5:4
Loop clock PLL data register pointer
Since the pointers are auto-incremented, the most efficient way to program the pixel clock PLL is to first write
zeros to bits 1 and 0 of the PLL control register, followed by three consecutive writes to the pixel clock PLL
data register to program the N, M, and P values. Following the third write, the pixel clock PLL pointer points
to the read-only status register, while the MCLK and loop clock PLL pointers point to the corresponding 7-bit
N value registers. Two more sets of three consecutive writes to the MCLK and loop clock PLL data registers
can be performed, or writes to the PLL registers can be discontinued. Note that these operations do not have
to start with the pixel clock PLL data register. The pixel clock PLL can be output on the PCLKOUT terminal
by programming the pixel clock PLL P value register bit 3 to a logic 1.
The frequency of the voltage controlled oscillator (VCO) is given by:
F
VCO
= F
REF
x ((M + 2)
×
8) / (N + 2)
Provided:
F
REF
/ (N + 2)
110 MHz
N, M
0.5 MHz and
(F
VCO
)
220 MHz and
1
Then the PLL output frequency is :
F
PLL
= F
VCO
/ 2
P
The MCLK and DCLK outputs are further divided and controlled by the MCLK/DCLK control register as
detailed in Table 2–6.
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
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