參數(shù)資料
型號(hào): TVP3025-175
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE(三PLL,視頻接口調(diào)色器)
中文描述: 視頻接口盒(三鎖相環(huán),視頻接口調(diào)色器)
文件頁(yè)數(shù): 47/99頁(yè)
文件大小: 663K
代理商: TVP3025-175
2–33
displayed instead of direct color. Therefore, when programming the device for any direct-color mode, both
the color-key-control and auxiliary-window registers must be set such that direct-color graphics is displayed.
For true color (gamma corrected through the palette), one of the functions must be set to palette graphics.
If VGA switching is performed, it is recommended that the VGA blank and sync signals also be utilized.
2.3.10.1 VGA Switch Control Register
The VGA switch control register provides synchronization functions needed to allow VGA switching with
multiplexed pixel modes. Resynchronization of the internal clock counters to the VGA blank or sync control
signals is provided so that the first VGA pixel coming out of blank always aligns with the first pixel in a group
of data latched on LCLK. Also, the register allows adjustment of the VGA pipeline delay to account for the
differences associated with multiplexed pixel port modes. This register is detailed below.
BIT NAME
VALUES
DESCRIPTION
VSCR4
1: Enable
Divider synchronization enable. If this bit is set to logic 1,
resynchronization of the clock counters is enabled.
0: Disable (default)
VSCR3
1: Rising edge
Divider reset control edge. Determines which edge of the signal set by
VSCR2 is used.
0: Falling edge
VSCR2
1: VGAHS
Divider reset control input. This bit determines whether VGA sync or
blank resynchronizes the clock counters.
0: VGABL
VSCR1 0
VSCR1, 0
11: +6, for 4:1 multiplexing
VGA pipeline delay control Allows adjustment of the VGA pipeline
VGA pipeline delay control. Allows adjustment of the VGA pipeline
delay for different pixel port multiplexing modes.
10: +2, for 2:1 multiplexing
00: +0, for 1:1 multiplexing
2.3.10.2 Windowing Control
The TVP3025 supports several windowing formats. These are specified by the auxiliary-control register
bits 0–2 and PSEL as shown below.
Window context switching is determined by the following equation:
SWITCH = [(PSEL
×
ACR2) + (WINDOW
×
ACR1)]
ACR0
where:
WINDOW = 1 inside the auxiliary window.
ACRnis the nth bit of the auxiliary-control register.
The following table then applies:
MULTIPLEX MODE SELECTED
DISPLAY RESULT
SWITCH = 0
Direct-color
Direct-color
SWITCH = 1
VGA
Overlay
Direct-color with VGA
Direct-color
NOTES: 18. The multiplex mode is set by multiplex-control registers 1 and 2. If VGA switching is desired, multiplex-
control register 2 bit 7 needs to be set to a logic 1 to enable the VGA port and the desired direct-color mode
must be chosen with the remaining MCR bits. For example, if direct-color mode 1 is chosen and multiplex-
control register 2 is normally set to 1B (hex), it would instead be set to 9B (hex) for VGA switching.
19. The DAC output is undefined if SWITCH = 1 when doing overlay switching in a direct-color mode that does
not have overlay capability.
20. Auxiliary-control register bits ACR2 and ACR1 can be used to independently enable or disable the
port-select and windowing functions as shown in the equation above. If both switching functions are
disabled, ACR0 is used to default the display to either direct color or palette graphics. Palette graphics are
either VGA or overlay if in a direct-color mode or pseudo-color when in the pseudo-color mode. The reset
default is for palette graphics to be displayed–as needed for the VGA pass-through mode.
21. The device supports switching when using multiplexing modes. However, caution must be observed when
using the port select function with the multiplexing modes other than 1:1, since the PSEL signal is latched
on LCLK (same as the pixel port).
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