參數(shù)資料
型號(hào)： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁數(shù)： 80/99頁
文件大?。?/td> 663K
代理商： TVP3025-175
3–4
3.5 Timing Requirements (see Note 5)
TVP3025
-135
MIN
TVP3025
-175
MIN
TVP3025
-220
MIN
UNIT
MAX
MAX
MAX
DOTCLK frequency
135
175
220
MHz
Pixel clock PLL
Internal frequency
135
175
220
MHz
PCLKOUT frequency
110
110
110
MHz
CLK0 frequency for VGA pass-through mode
(see Note 6)
85
85
85
MHz
tcyc
Clock cycle time
TTL
7.4
7.1
7.1
ns
ECL
7.4
5.8
4.54
tsu1
th1
tsu2
th2
Setup time, RS(0 – 3) valid before RD or WR
↓
Hold time, RS(0 – 3) valid after RD or WR
↓
Setup time, D(0 – 7)valid before WR
↑
Hold time, D(0 – 7)valid after WR
↑
Setup time, VGA(0 – 7) and VGAHS, VGAVS, and
VGABL valid before CLK0
↑
(see Note 7)
10
10
10
ns
10
10
10
ns
35
35
35
ns
0
0
0
ns
tsu3
2
2
2
ns
th3
Hold time, VGA(0 – 7) and VGAHS, VGAVS, and
VGABL valid after CLK0
↑
(see Note 7)
Setup time, P(0 – 63) and PSEL valid before LCLK
↑
(see Note 8) SYSHS, SYSVS, SYSBL
2
2
2
ns
tsu4
2
2
2
ns
th4
Hold time, P(0 – 63) and PSEL valid after LCLK
↑
(see Note 8) SYSHS, SYSVS, SYSBL
1
1
1
ns
tsu5
Setup time, SYSHS, SYSVS, and SYSBL valid
before VCLK
↓
(VCLK lactched)
5
5
5
ns
th5
Hold time, SYSHS, SYSVS, and SYSBL valid after
VCLK
↓
(VCLK lactched)
1
1
1
ns
tw1
tw2
Pulse duration, RD or WR low
50
50
50
ns
Pulse duration, RD or WR high
30
30
30
ns
tw3
Pulse duration clock high
Pulse duration, clock high
TTL
3
3
3
ns
ECL
3
2.5
2
tw4
Pulse duration clock low
Pulse duration, clock low
TTL
3
3
3
ns
ECL
3
2.5
2
tw5
tw6
NOTES:
Pulse duration, SFLAG high (see Note 9)
30
30
30
ns
Pulse duration, SCLK high (see Note 9)
5. TTL input signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels unless
otherwise specified. ECL input signals are VDD–1.8 V to VDD–0.8 V with less than 2 ns rise/fall time
between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and
90% signal levels. Analog output loads are less than 10 pF. D<0:7> output loads are less than 50 pF. All
other output loads are less than 50 pF unless otherwise specified.
6. In VGA mode, CLK0 minimum pulse duration for clock low should be greater than 4.8 ns. If VGA switching
is to be performed using self-clocked timing, the maximum pixel rate cannot exceed 50 MHz.
7. Reference to CLK0 input only.
8. RCLK is delayed from SCLK in such a way that when RCLK is connected to LCLK, the timing is essentially
the same as the TLC3407x family of parts.
9. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See
Section 2.3.7.2 for details.
15
55
15
55
15
55
ns
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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