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參數(shù)資料
| 型號： | TVP3025-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 73/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-175 |
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2–59
2.4.15.5 Command Register 4 (RS value = 11010, when CR07 = logic 1)
Table 2–27. Command Register 4 (RS value = 11010)
BIT
NAME
VALUES
DESCRIPTION
CR47
Reserved (logic 0)
CR46
Reserved (logic 0)
CR45
Reserved (logic 0)
CR44
Reserved (logic 0)
CR43
0: GP I/O4 disabled (default)
This bit enables or disables general-purpose I/O bit GP I/O4 for output.
When it is disabled the terminal is tri-state like the other GP I/O terminals
When it is disabled, the terminal is tri-state like the other GP I/O terminals.
This can possibly be used to drive RS4 input.
1: GP I/O4 enabled for output
CR42
0: GP I/O4 = logic 0 (default)
GP I/O4 input value. When CR43 is set to a logic 1, GP I/O4 is enabled as
an output. The logic signal provided by this bit is output on GP I/04.
1: GP I/O4 = logic 1
CR41
Reserved (logic 0)
CR40
0: 32-bit pixel bus
1: 64-bit pixel bus
Pixel bus width select. This bit sets the pixel bus width to either 32 bits or
64 bits. See Table 2–18 and Section 2.4.10.
NOTE: The following command register 4 bits are written into the following TVP3025 indirect register bits: CR40 into
multiplexer-control register 2 bits 0, 1, and 2; CR40 into output-clock-selection register bit 7, CR40 into true color
control register bit 2, CR40 into auxiliary control register bit 3, CR42 into general-purpose I/O data register
bit 4, CR43 into general-purpose I/O control register bit 4.
These registers are not initialized at power up. All command registers are set to a logic 0 when a low signal is
asserted at the RESET terminal.
When command register 4 is written, 003F (hex) is loaded into the TVP3020 sprite-origin x and y registers
(index 04 and 05 hex) and the cursor addressing is set to planar format (cursor-control register
bit 7 = logic 1) to provide cursor positioning similar to the BT485. If these indexed registers are subsequently
overwritten in the TVP3020 mode and then the device is operated in the BT485 mode, they must be reset
to proper BT485 values. This can be accomplished by writing to those registers in the TVP3020 mode,
performing a BT485 register initialization by resetting the device with the MODE1 terminal high or by writing
to command register 4.
When command register 4 is written, miscellaneous-control register bit 6 is set to logic 1 to enable SYSBL,
SYSHS, and SYSVS latching on LCLK. This also occurs when the device is reset with MODE1 terminal high.
Command register 4 bit CR40 sets the output-clock-selection register bit 7 to logic 1, which further divides
the RCLK by 2 because of the higher multiplexing rate used in the 64-bit modes. See Table 2–7 notes.
2.4.16
2.4.16.1 Pixel Read-Mask Register (RS value =10010)
The 8-bit pixel read-mask register can be written to or read by the MPU at any time and is not initialized at
power up. The contents of this register are bit-wise ANDed with the pixel data prior to addressing the color
palette RAM. The pixel read-mask register is initialized to logic ones using the RESET terminal.
Internal Registers
2.4.16.2 Status Register (RS value = 11010)
The 8-bit status register monitors certain device states and identifies devices. It can be read by the MPU
at any time; MPU write cycles are ignored. This register is not reset during power up or at reset.
相關(guān)PDF資料 |
PDF描述 |
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| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-135AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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