參數(shù)資料
型號(hào)： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁(yè)數(shù)： 54/99頁(yè)
文件大?。?/td> 663K
代理商： TVP3025-175
2–40
2.3.17.2 Main Differences from the TVP3020
Horizontal zooming implementation has been changed to a more efficient method. The zooming
function must be programmed differently than on the TVP3020. See Section 2.3.12 for details.
Multiplex-control register 1, bit 3 must now be set to logic 1 for proper true color and direct color
operation when in the TVP3025 mode. See Table 2–8 for proper register settings.
If the device is reset to the BT485 mode, to program the multiplexer for the TVP3020 true-color
modes, true-color control register bit 2 must be set to a logic 0. This is automatically the case if
the device is reset into the TVP3020 mode.
Frame buffer interface timing modes are simplified. See Section 2.3.7.
2.3.18
2.3.18.1 General-Control Register (Index 1D hex)
Miscellaneous Control Register Bit Definitions
Table 2–12. General-Control Register
BIT
NAME
VALUES
DESCRIPTION
GCR7
0: (default)
Overscan-control signal no longer used It should be left as logic 0
Overscan-control signal no longer used. It should be left as logic 0.
1:
GCR6
0: Disable (default)
Overscan enable. Specifies whether to enable the user-defined overscan
Overscan enable. Specifies whether to enable the user defined overscan
screen borders.
1: Enable
GCR5
0: Disable
Sync enable. This bit specifies whether SYNC information is to be output onto
IOG.
1: Enable (default)
GCR4
0: 0 IRE (default)
Pedestal control. This bit specifies whether a 0 or 7.5 IRE blanking pedestal
is to be generated on the video outputs.
1: 7.5 IRE
GCR3
0: Little-endian (default)
Little-endian/big-endian select. Selects either little- or big-endian format for the
Little endian/big endian select. Selects either little or big endian format for the
pixel-bus interface.
1: Big-endian
GCR2
0: Disable (default)
Split shift-register-transfer enable See Section 2 3 7 2
Split shift-register-transfer enable. See Section 2.3.7.2.
1: Enable
GCR1
0: Active (low) (default)
VSYNCOUT output polarity.
1: Active (high)
GCR0
0: Disable (default)
1: Enable (high)
HSYNCOUT output polarity.
NOTE: BT485 command register bit CR03 is written to GCR5 and CR05 to GCR4 in the BT485 mode of operation.
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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