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參數(shù)資料
| 型號： | TVP3025-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 22/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-175 |
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2–8
Table 2–5. Input-Clock-Selection Register (Index 001A)
INPUT-CLOCK-SELECTION REGISTER (HEX)
(see Note 1)
FUNCTION (see Note 2)
00
Select CLK0 as clock source
01
Select CLK1 as clock source
02
Select CLK2 as TTL clock source
03
04
05
Select CLK2 as TTL clock source
Select CLK2 and CLK2 as ECL clock source
Select pixel clock PLL as clock source
10
Select CLK0 as doubled clock source
11
Select CLK1 as doubled clock source
12
Select CLK2 as TTL doubled clock source
13
Select CLK2 as TTL doubled clock source
14
Select CLK2/CLK2 as ECL doubled clock source
CLK0 is chosen at RESET as required for VGA pass-through.
NOTES:
1. Register bits 3 through 7 are reserved.
2. When the clocks are selected from one input clock source to another, a minimum of 30 ns is needed
before the new clocks are stabilized and running.
2.3.4
PLL Clock Generators
In addition to externally supplied clock sources, the TVP3025 has three on chip, fully programmable,
frequency synthesis phase-locked loops (PLLs). The first (pixel clock) PLL is intended for pixel clock
generation for frequencies up to the device limit. The second (MCLK) PLL is provided for general system
clocking such as memory clock, and the third PLL (called the loop clock PLL) is useful for synchronizing pixel
data and latch timing by minimizing loop delay. The loop clock PLL is discussed in detail in Section 2.3.7.4.
The clock generators use a modified M over (N x 2
P
) scheme to enable a wide range of precise frequencies.
The advanced PLLs utilize an internal loop filter to provide maximum noise immunity and reduce jitter.
Except for the reference crystal or oscillator, no external components or adjustments are necessary. Each
PLL can be independently enabled or disabled for maximum system flexibility. Additionally, a separate
MCLK/DCLK control register (index 0039) is provided to allow further frequency division and indepedent
control of the MCLK and DCLK outputs. Figure 2–1 illustrates the TVP3025 PLL clocking tree for the pixel
clock and MCLK generators.
RCLK
Divider
VCLK
Divider
Pixel Clock
PLL
MCLK
PLL
MCLK
Divider
DCLK
Divider
Crystal
Amplifier
RCLK
VCLK
MCLK
DCLK
Internal
Pixel Clock
CLK0x
XTAL2
XTAL1
Figure 2–1. Pixel Clock PLL and MCLK PLL Clocking Tree
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-135AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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