參數(shù)資料
型號(hào)： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁數(shù)： 24/99頁
文件大小： 663K
代理商： TVP3025-175
2–10
Table 2–6. MCLK/DCLK Control Register (Index 0039 hex)
BIT NAME
VALUES
DESCRIPTION
MDCR7
0: Disable (default)
1: Enable
DCLK output enable bit.
MDCR6,
MDCR5, MDCR4
000: Divide by 2 (default)
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 10
101: Divide by 12
110: Divide by 14
111: Divide by 16
DCLK divide ratio. These bits specify the factor by which the MCLK
PLL is divided by before being output on the DCLK output terminal.
MDCR3
0: Disable
1: Enable (default)
MCLK output enable bit.
MDCR2,
MDCR1, MDCR0
000: Divide by 2 (default)
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 10
101: Divide by 12
110: Divide by 14
111: Divide by 16
MCLK divide ratio. These bits specify the factor by which the MCLK
PLL is divided by before being output on the MCLK output terminal.
Divide ratios are identical to those specified by bits MDCR6–MDCR4
for the DCLK divider.
If P value register bit 7 is set to logic 0, then the PLL is disabled upon writing to the corresponding N value
register, and the PLL is enabled upon writing to the corresponding P value register. If the P value register
bit 7 is set to logic 1, then the PLL is always enabled. If the pixel clock PLL is to be used for pixel clock
generation after it has been programmed, the input clock selection register must be set to 05 (hex).
At device reset, the loop clock PLL is disabled and reset, while the MCLK PLL and pixel clock PLL are
programmed to give approximately 45 MHz and 25 MHz outputs, respectively with a standard 14.318 MHz
crystal reference. For MCLK M = 9, N = 5, P = 1, MCLK/DCLK control = 08 (hex). For pixel clock M = 5,
N = 6, P=2.
All PLLs should be programmed such that F
REF
/(N + 2)
proper operation. Also, N and M should be minimized, but
1 MHz and 110 MHz
1.
(F
VCO
)
220 MHz for
For pixel clock PLL output on the PCLKOUT terminal, the pixel clock P value register bit 3 must be set to
logic 1.
For the pixel clock PLL to be used as the pixel clock source, it must be selected in the input clock selection
register (see Section 2.3.3).
If the MCLK PLL is used to clock the graphics controller, in general, the P value register bit 7 should be set
to logic 1 the first time the PLL is written so that the PLL always remains enabled. Otherwise, system lock-up
could occur.
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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