參數(shù)資料
型號： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁數(shù)： 31/99頁
文件大?。?/td> 663K
代理商： TVP3025-175
2–17
Loop Clock
PLL
D Q
D Q
D Q
LCLK
RCLK
′
RCLK
Divider
Dot Clock
Generator
Dot
Clock
Input Data Latch Structure
TVP3025
RCLK
CLKx
LCLK
P(0–63)
Graphics
Accelerator
VRAM
Figure 2–7. Loop Clock PLL Operation
As an example of using the loop clock PLL, consider the case where the pixel clock is running at 128 MHz,
and the device is configured for a 64-bit pixel bus, 8-bits/pixel, and 8:1 multiplexing. First the output-clock-
selection register should be programmed to 03 (hex) to divide the internal RCLK (see Figure 2–8) by eight.
No programming of the output-clock-selection register is needed in the BT485 mode of operation. Then the
loop clock PLL N and M value registers should be set to 1. Closed loop PLL dynamics will tend to force the
LCLK frequency (derived from the generated RCLK) to equal the RCLK frequency. The P value is chosen
such that, for F
LCLK
= F
RCLK
, the VCO will run in the 110 – 220 MHz range. For this example, the RCLK
frequency is simply 128 MHz/8 = 16 MHz. For F
LCLK
= F
RCLK
, the loop clock PLL needs to generate a signal
equal in frequency to RCLK = 16 MHz. Therefore, in order to keep the VCO in the 110–220 MHz range, the
P value must be set to 3. Since F
PLL
= F
VCO
/ 2
P
(F
VCO
= F
PLL
×
2
P
), the VCO frequency will be 128 MHz.
Some graphics controllers internally divide down the RCLK frequency to produce the LCLK. This affects the
P value that must be chosen for the loop clock PLL. It does not affect the RCLK divide ratio chosen in the
output-clock-selection register, so this should not be changed. For example consider the case above, but
with the graphics controller further dividing the generated RCLK reference by eight to produce the LCLK
signal. The output-clock-selection register is still programmed to divide by eight, and the M and N PLL values
are still set to 1. Again, loop dynamics tend to force F
LCLK
= F
RCLK
= 16 MHz. For F
LCLK
= 16 MHz, the
generated RCLK frequency must be eight times this due to the divide by eight in the graphics controller.
Therefore, in order to keep the VCO in the 110–220 MHz range, the P value must be set to 0.
Since the maximum P value is 3 ( giving 2
P
= 8) and the minimum VCO frequency is 110 MHz, the minimum
RCLK frequency that can be generated using the loop clock PLL is 13.75 MHz. For those modes where a
lower RCLK frequency is needed, the loop clock PLL is not used, and RCLK is determined from the
output-clock-selection register (or multiplexing mode selected in the BT485 mode). Loop delay is not a
problem in these cases, since the LCLK signal is at such a low frequency.
Many very efficient graphics system typologies are possible using the loop clock PLL to synchronize the
system timing. Implementations are shown in Figures 2–8 and 2–9. Figure 2–8 shows the typical device
connection, with PCLKOUT supplying the pixel clock source. If the loop clock PLL is enabled, VGA
frequencies over 100 MHz can be achieved. If the loop clock PLL is not enabled, VGA is limited to
approximately 25 MHz due to the loop delay in the system. For the highest frequency VGA support, the
topology depicted in Figure 2–9 can be utilized, but this requires the use of an external multiplexer.
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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