參數(shù)資料
型號(hào)： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁數(shù)： 29/99頁
文件大?。?/td> 663K
代理商： TVP3025-175
2–15
2.3.7.2
When SCLK is used, the TVP3025 has direct support for split shift-register-transfer (SSRT) VRAMs. In order
to allow the VRAMs to perform a split shift-register transfer, an SCLK pulse must be inserted during the blank
sequence. This causes the first group of pixel data to appear at the pixel port during blank and allows the
first group of data to be displayed as soon as the TVP3025 comes out of blank. When the VRAM split
shift-register operation is performed, the SCLK timing is adjusted to work with the SFLAG input. Figure 2–5
shows timing using the SSRT function. When a rising edge occurs on the SFLAG input, one SCLK with a
minimum of 15 ns pulse width is generated within the specified delay. The SSRT generated SCLK replaces
the first SCLK in the regular shift register transfer case as shown in Figures 2–3 and 2–4.
Split Shift-Register-Transfer Support
Note that the SSRT enable bit (bit 2) in the general-control register must be set to a logic 1. The SFLAG
minimum duration and other timing requirements and specifications are given in Sections 3.5 and 3.6.
VCLK
In Phase
SYSBL
at Input Terminal
RCLK
Internal Delayed
LCLK = RCLK
BLNK
(internal signal
before DOTCLK
pipeline delay)
PIXEL DATA
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch Second Group of Pixel Data
Latch Last Group
of Pixel Data
SFLAG Input
Last
Group
2nd
Group
3rd
Group
4th
Group
5th
Group
6th Group
1st Group of
Pixel Data
SCLK Between Split Shift Register and Regular Shift Register Transfer
Latch First Group of Pixel Data
Figure 2–5. Frame Buffer Timing With SSRT (VCLK Latched Blank)
(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)
2.3.7.3
For those systems where the color palette data latch clock (LCLK) and VRAM shift clock are generated by
the graphics controller, the TVP3025 SCLK output cannot be utilized. In these systems, RCLK should be
connected to the graphics controller to provide the timing reference for clock generation. Additionally,
auxiliary control register bit 3 should be set to a logic 0 so that the video control signals SYSBL, SYSHS,
and SYSVS are aligned with pixel data. These video control signals should be latched on LCLK like the pixel
data, so miscellaneous-control register bit 6 should be set to logic 1. Figure 2–6 shows typical frame buffer
timing for this case.
Frame Buffer Timing Without Using SCLK
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*