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參數(shù)資料
| 型號(hào)： | VCT3801A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video/Controller/Teletext IC Family |
| 中文描述： | 視頻/控制/圖文電視IC系列 |
| 文件頁數(shù)： | 11/172頁 |
| 文件大小： | 2243K |
| 代理商： | VCT3801A |
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ADVANCE INFORMATION
VCT 38xxA
Micronas
11
2. Video Processing
2.1. Introduction
The VCT 38xxA includes complete video, display, and
deflection processing. In the following sections the
video processing part of the VCT 38xxA will be named
VDP for short.
All processing is done digitally, the video front-end and
video back-end are interfacing to the analog world.
Most functions of the VDP can be controlled by soft-
ware via I
2
C bus slave interface (see Section 2.15. on
page 32).
2.2. Video Front-end
This block provides the analog interfaces to all video
inputs and mainly carries out analog-to-digital conver-
sion for the following digital video processing. A block
diagram is given in Fig. 2–1.
Most of the functional blocks in the front-end are digi-
tally controlled (clamping, AGC, and clock-DCO). The
control loops are closed by the Fast Processor (‘FP’)
embedded in the video decoder.
2.2.1. Input Selector
Up to seven analog inputs can be connected. Four
inputs are for input of composite video or S-VHS luma
signal. These inputs are clamped to the sync back
porch and are amplified by a variable gain amplifier.
Two chroma inputs can be used for connection of
S-VHS carrier-chrominance signal. These inputs are
internally biased and have a fixed gain amplifier. For
analog YC
r
C
b
signals (e.g. from DVD players) one of
the selected luminance inputs is used together with
CBIN and CRIN inputs.
2.2.2. Clamping
The composite video input signals are AC-coupled to
the IC. The clamping voltage is stored on the coupling
capacitors and is generated by digitally controlled cur-
rent sources. The clamping level is the back porch of
the video signal. S-VHS chrominance is also AC-cou-
pled. The input pin is internally biased to the center of
the ADC input range. The chrominance inputs for
YC
r
C
b
need to be AC-coupled by 220 nF clamping
capacitors. It is strongly recommended to use 5-MHz
anti-alias low-pass filters on each input. Each channel
is sampled at 10.125 MHz with a resolution of 8 bit and
a clamping level of 128.
2.2.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
The gain of the video input stage including the ADC is
213 steps/V with the AGC set to 0 dB. The gain of the
chrominance path in the YC
r
C
b
mode is fix and
adapted to a nominal amplitude of 0.7 V
pp
. However, if
an overflow of the ADC occurs an extended signal
range from 1 V
pp
can be selected.
2.2.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit res-
olution. An integrated bandgap circuit generates the
required reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
Fig. 2–1:
Video front-end
VIN2
VIN3
VIN4
CIN1
VIN1
Bias
ADC
ADC
Gain
Clamp
I
Frequency
Reference
Generation
DVCO
±
150
ppm
AGC
+6/–4.5 dB
digital CVBS or Luma
digital Chroma
System Clocks
20.25 MHz
CVBS/Y
CVBS/Y
CVBS/Y
CVBS/Y
Chroma
M
CIN2
CRIN
Chroma
Clamp
CBIN
Chroma
m
VOUT
CVBS/Y
3
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