參數(shù)資料
型號(hào): VCT3801A
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video/Controller/Teletext IC Family
中文描述: 視頻/控制/圖文電視IC系列
文件頁數(shù): 38/172頁
文件大小: 2243K
代理商: VCT3801A
VCT 38xxA
ADVANCE INFORMATION
38
Micronas
h’18
h’19
h’1a
h’1d
h’1c
h’1b
8
r
measurement result registers
minimum in active picture
maximum in active picture
white drive
cutoff/leakage red
cutoff/leakage green
cutoff/leakage blue,
read pulse starts tube measurement
MRMIN
MRMAX
MRWDR
MRCR
MRCG
MRCB
h’1e
8
r
measurement adc status and Fast-Blank input status
measurement status register
bit [0]
0/1
bit [2:1]
00
01
10
11
bit [3]
0/1
bit [4]
0/1
bit [5]
1
tube measurement active / complete
white drive measurement cycle
red
green
blue
reserved
picture measurement active / complete
Fast-Blank input Low / High (static)
Fast-Blank input negative transition since
last read (bit reset at read)
reserved
bit [7:6]
PMS
Vertical Timing
h’67
9
w v
vertical blanking start
bit [8:0]
0..511
first line of vertical blanking
305
VBST
h’77
9
w v
vertical blanking stop
bit [8:0]
0..511
last line of vertical blanking
25
VBSO
h’5f
9
w v
vertical free run period
bit [8:0] free running field period = (value+4) lines
309
VPER
Horizontal Deflection and Timing
h’7a
9
w v
quadratic term of angle & bow correction
bit [8:0]
256..+255
(
±
500 ns)
0
BOW
h’76
9
w v
linear term of angle & bow correction
bit [8:0]
256..+255
(
±
500 ns)
0
ANGLE
h’6e
9
w v
adjustable delay of PLL2, clamping, and blanking (relative to
front sync)
adjust clamping pulse for analog RGB input
bit [8:0]
256..+255
(
±
8
μ
s)
141
POFS2
h’72
9
w v
adjustable delay of flyback, main sync, csync and analog RGB
(relative to PLL2)
adjust horizontal drive or csync
bit [8:0]
256..+255
(
±
8
μ
s)
0
POFS3
h’7e
9
w v
adjustable delay of main sync (relative to flyback)
adjust horizontal position for digital picture
bit [8:0]
20 steps
=
1
μ
s
120
HPOS
h’5b
9
w v
start of horizontal blanking
bit [8:0]
0..511
1
HBST
I
2
C Sub
address
Number
of bits
Mode
Function
Default
Name
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