ADVANCE INFORMATION
VCT 38xxA
Micronas
125
5.17.5.ADC Registers
A write access to register AD0 starts the A/D conver-
sion of the written channel number and sampling dura-
tion. The flag EOC signals the end of conversion. The
result is stored in register AD1 (bit 9 to 2) and in regis-
ter AD0 (bit 1 and 0).
EOC
r1:
r0:
End of Conversion
End of conversion
Busy
EOC is reset by a write access to the register AD0.
EOC must be true before starting the first conversion
after enabling the module by setting SR1.ADC.
CMPO
r1:
r0:
Comparator Output
Input is lower than reference voltage.
Input is higher than reference voltage.
TSAMP
Sampling Time
TSAMP adjusts the sample time and the conversion
time. The total conversion time is 20 clock cycles
longer than the sample time. Sampling starts one clock
cycle after completion of the write access to AD0.
CHANNEL Channel of Input Multiplexer
CHANNEL selects from which port pin the conversion
is done. The MSB of CHANNEL is bit 3. No port pin is
connected to the ADC if the channel 0 is selected. In
this case the input of the A/D converter is connected to
ground. After reset, CHANNEL is set to zero.
AN 9 to 0
Analog Value Bit 9 to 0
The 10 bit analog value is in the range of 0 to 1023.
The 8 MSB can be read from register AD1. The two
LSB can be read from register AD0. The result is avail-
able until a new conversion is started.
280:
1FA8
281:
AD0
282:
ADC Register 0
bit
7
6
5
4
3
2
1
0
r
EOC
CMPO
x
x
x
x
AN1
AN0
w
TSAMP
CHANNEL
reset
0
0
0
0
0
0
0
0
283:
1FA9
284:
AD1
285:
ADC Register 1
bit
7
6
5
4
3
2
1
0
r
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
reset
Table 5–20:
Sampling time adjustment
TSAMP
t
Sample
t
Conversion
0H
20 T
OSC
40 T
OSC
1H
60 T
OSC
80 T
OSC
2H
140 T
OSC
160 T
OSC
3H
300 T
OSC
320 T
OSC
Table 5–21:
ADC input multiplexer
CHANNEL
Port Pin
0
none
1
P10
2
P11
3
P12
4
P13
5
P14
6
P15
7
P16
8
P17
9
P20
10
P21
11
P22
12
P23
13
P24
14
P25
15
P26