VCT 38xxA
ADVANCE INFORMATION
50
Micronas
3.5.2. Memory Organization
The upper end of the memory is defined by the SRAM
size, the lower end can be defined with the
PAGE_MEMORY
command. Default memory organi-
zation is shown in Fig. 3–4.
Fig. 3–4:
Memory organization
The memory organization depends on available SRAM
size. If external SRAM is not available, there is only
one display bank for OSD and teletext and the page
memory starts at a different location (see Table 3–1).
3.5.3. Page Table
The memory management is based on a fixed size
page table, which has entries for every hexadecimal
page number from 100 to 8FF. The page table starts
with page 800 and contains a 2-Byte page pointer for
every page.
The page table can be read with the command
READ_PAGE_INFO
sending the page number and
reading the 2-Byte page pointer containing:
– SRAM pointer
– cycle flag
– memory flag
– subpage flag
– update flag
– protection flag
The SRAM pointer gives the location where the page
is stored in memory. The page size is fixed to 1 kByte,
only ghost rows are allocated dynamically.
The cycle flag will be set as soon as this page is
detected in the transmission cycle even if it cannot be
stored in memory. Only if the page is really stored in
memory, the memory flag will be set. The subpage flag
will be set for every page in cycle if the page subcode
is different from 0000H or 3F7FH. The update flag is
set every time a page is stored and will be reset only
for the display page after updating the display memory.
A page with protection flag set will never be removed
from memory.
The memory manager uses page priorities to decide
which pages should be stored or removed from mem-
ory. If no more memory is available, pages with lowest
priority are removed automatically and the higher prior-
ity pages are stored at their place. By setting the page
priority the programmer has control over the memory
management.
The page table is fully controlled by the memory man-
ager and should never be written by external software.
To change the page table flags the command
CHANGE_PAGE_INFO
can be used.
Table 3–1:
Memory Organisation
Memory
Segment
Address
SRAM Size
≥
128k
19k
16k
3k
Display Bank
h’3000
h’4000
h’3000
h’0000
TTX Bank
h’2000
h’4000
h’3000
h’0000
Page Table
h’0000
h’0000
h’0000
no
Acquisition Scratch
h’1000
h’1000
h’1000
no
Page Memory
h’4000
h’1800
h’1800
no
08 00 00 = 4Mbit
02 00 00 = 1Mbit
00 80 00 = 256Kbit
00 40 00
00 30 00
00 20 00
00 10 00
00 00 00
4 kBytes
TTX Display Bank
n x 1 kByte
Page Memory
SRAM
4 kBytes
Display Bank
4 kBytes
Page Table
4 kBytes
Acquisition
Scratch