參數(shù)資料
型號： VCT3801A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video/Controller/Teletext IC Family
中文描述： 視頻/控制/圖文電視IC系列
文件頁數(shù)： 93/172頁
文件大?。?/td> 2243K
代理商： VCT3801A
ADVANCE INFORMATION
VCT 38xxA
Micronas
93
5.7.3.3. Watchdog
The Watchdog module serves to monitor undisturbed
program execution. A failure of the program to retrigger
the Watchdog within a preselectable time will pull the
RESQ pin low and thus reset the VCT 38xxA (see Fig.
5–3 and Fig. 5–4). The Watchdog reset source is only
enabled after the first write access to register CSW1
(see Section 5.7.3.2. on page 92).
Once the Watchdog is enabled, it cannot be dis-
abled anymore, neither by software nor by pulling
down the external RESQ pin. Only after power up
the watchdog is disabled.
Fig. 5–4:
Block diagram of watchdog
The Watchdog contains a down-counter that gener-
ates a reset when it wraps from zero to FFh. It is
reloaded with the content of the watchdog timer regis-
ter, when, on a write access to register CSW1, watch-
dog trigger registers 1 and 2 contain bit complemented
values. Resetting the VCT 38xxA initializes the watch-
dog timer register to FFh, thus forcing the Watchdog to
create a maximum reset interval.
The Watchdog is controlled by register CSW1. The
first write access to it loads the timer register value set-
ting the Watchdog’s unretriggered reset interval. The
desired interval can be programmed by setting the
CSW1 value to:
The resolution of the Watchdog is 8192/f
CPU
. In CPU
Slow mode (see Section 5.2.1. on page 86), the watch-
dog is clocked with the reduced CPU clock.
The second and all following even numbered write
accesses load watchdog trigger register 1, the third
and all following odd numbered write accesses load
watchdog trigger register 2.
In all future, the CPU has to write alternatingly to regis-
ter CSW1 value and bit complement value, thus retrig-
gering the up-counter. Failure to retrigger will result in
an overflow of the up-counter generating a Watchdog
reset.
It is not allowed to change a chosen value. Writing a
wrong value to CSW1 immediately sets the flag
CSW1.WDRES and prohibits further retriggering of the
watchdog counter.
CSW1.WDRES is true after a Watchdog reset. Only a
Supply Supervision reset or a write access to register
CSW1 clears it.
Trigger Reg1
Timer Register
Trigger Reg2
8-Bit-Counter
2.write
& even
3.write
& odd
1. write
8
≥
1
8
8
zero
reset out
load
reset in
write CSW1
power on
S Q
R
CSW1.WDRES
CSW1
CSW1
CSW1
&
S Q
R
&
=
1. write
≥
1
clk = f
CPU
/8192
1. write
C
S
Q
≥
1
&
D
2.write & even
3.write & odd
Value
Interval
-----------------------------------
f
×
8192
1
–
=
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