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VCT 38xxA
ADVANCE INFORMATION
98
Micronas
If the mapping logic does not find any address match,
the TPU address is directly put on the CPU address
bus with A19 set to “1”. In case of multiple matches,
the priority is map1 > map2 > map3 > map4.
Fig. 5–9:
DMA mapping logic
5.9.1. DMA Registers
MA19 to 8
TPU address is masked with this value.
Mask Address
CA19 to 8
Masked TPU address is compared with this value.
Compare Address
MPA19 to 8 Map Address
Matching TPU address is replaced with this value.
DMAEN
w1:
w0:
DMA Enable
Enable DMA Interface
Disable DMA Interface
MAPxE
w1:
w0:
Mapping Logic x Enable
Enable mapping logic x
Disable mapping logic x
40:
1E00
41:
MASK1L
42:
Mask 1 Low Byte
43:
1E01
44:
MASK2L
45:
Mask 2 Low Byte
46:
1E02
47:
MASK3L
48:
Mask 3 Low Byte
49:
1E03
50:
MASK4L
51:
Mask 4 Low Byte
bit
7
6
5
4
3
2
1
0
w
MA15
MA14
MA13
MA12
MA11
MA10
MA9
MA8
reset
1
1
1
1
1
1
1
1
52:
1E04
53:
MASK1H
54:
Mask 1 High Byte
55:
1E05
56:
MASK2H
57:
Mask 2 High Byte
58:
1E06
59:
MASK3H
60:
Mask 3 High Byte
61:
1E07
62:
MASK4H
63:
Mask 4 High Byte
bit
7
6
5
4
3
2
1
0
w
MA19
MA18
MA17
MA16
reset
1
1
1
1
64:
1E08
65:
CMP1L
66:
Compare 1 Low Byte
67:
1E09
68:
CMP2L
69:
Compare 2 Low Byte
70:
1E0A
71:
CMP3L
72:
Compare 3 Low Byte
73:
1E0B
74:
CMP4L
75:
Compare 4 Low Byte
bit
7
6
5
4
3
2
1
0
w
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
reset
1
1
1
1
1
1
1
1
&
=
≥
1
MASK n
CMP n
MAP n
match
&
&
A[19:8]
A[19:8]
n: mapping logic 1 to 4
12
12
12
12
76:
1E0C
77:
CMP1H
78:
Compare 1 High Byte
79:
1E0D
80:
CMP2H
81:
Compare 2 High Byte
82:
1E0E
83:
CMP3H
84:
Compare 3 High Byte
85:
1E0F
86:
CMP4H
87:
Compare 4 High Byte
bit
7
6
5
4
3
2
1
0
w
CA19
CA18
CA17
CA16
reset
1
1
1
1
88:
1E10
89:
MAP1L
90:
Map 1 Low Byte
91:
1E11
92:
MAP2L
93:
Map 2 Low Byte
94:
1E12
95:
MAP3L
96:
Map 3 Low Byte
97:
1E13
98:
MAP4L
99:
Map 4 Low Byte
bit
7
6
5
4
3
2
1
0
w
MPA15
MPA14
MPA13
MPA12
MPA11
MPA10
MPA9
MPA8
reset
1
1
1
1
1
1
1
1
100:
1E14
101:
MAP1H
102:
Map 1 High Byte
103:
1E15
104:
MAP2H
105:
Map 2 High Byte
106:
1E16
107:
MAP3H
108:
Map 3 High Byte
109:
1E17
110:
MAP4H
111:
Map 4 High Byte
bit
7
6
5
4
3
2
1
0
w
MPA19
MPA18
MPA17
MPA16
reset
1
1
1
1
112:
1E18
113:
DMAIM
114:
DMA Interface Mode
bit
7
6
5
4
3
2
1
0
w
DMAEN
MAP4E
MAP3E
MAP2E
MAP1E
reset
0
0
0
0
0