參數(shù)資料
型號: VCT3801A
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video/Controller/Teletext IC Family
中文描述: 視頻/控制/圖文電視IC系列
文件頁數(shù): 92/172頁
文件大小: 2243K
代理商: VCT3801A
VCT 38xxA
ADVANCE INFORMATION
92
Micronas
Fig. 5–3:
Block diagram of reset logic
5.7.3.1. Supply Supervision
An internal bandgap reference voltage is compared to
VSUP
S
. A VSUP
S
level below the Supply Supervision
threshold VREFPOR will permanently pull the pin
RESQ low and thus hold the VCT 38xxA in reset state
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
5.7.3.2. Clock Supervision
The Clock Supervision monitors the CPU clock fre-
quency f
CPU
. A frequency level below the clock super-
vision threshold of approx. 200 kHz will permanently
pull the pin RESQ low and thus hold the IC in reset
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
A frequency exceeding the specified clock frequency is
not detected.
Voltage
Supervision
&
>1
+
-
S Q
R
Clock
Supervision
Reset extension
16 or 4096
oscillator pulses
Watchdog
+
-
VSUP
S
V
REFPOR
Bandgap
V
REFA
V
REFR
V
REFPOR
V
REFA
V
REFR
RESQ
>1
&
CSW0.CSA
>1
+
-
>1
RESET
Interrupt
Source
RC.RESOUT
>1
CPU Reset
RC.RESDIS
VSUP
D
>1
TPU
Watchdog
RC
Reset
Control
reset
internal Reset to DMA, TPU, VDP
RC.VSI
RC.TPUI
RC.ALI
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