參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 101/124頁
文件大?。?/td> 1878K
代理商: 56F8014
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
101
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All the address and data buses described here are internal.
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1. In the formulas, T = clock cycle and T
osc
= oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz
(used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the 56F8014 internal reset stretching circuitry to extend this period to 2^21T.
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration
t
RA
4T
ns
Minimum GPIO pin Assertion for Interrupt
t
IW
2T
ns
10-6
RESET deassertion to First Address Fetch
3
t
RDA
96T
OSC
+ 64T
97T
OSC
+ 65T
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
t
IF
6T
ns
GPIO pin
(Input)
T
IW
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