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參數(shù)資料
| 型號(hào)： | 56F8014 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號(hào)控制器 |
| 文件頁(yè)數(shù)： | 43/124頁(yè) |
| 文件大?。?/td> | 1878K |
| 代理商： | 56F8014 |
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Functional Description
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
43
5.3.3
Fast interrupts are described in the
DSP56800E Reference Manual
. The interrupt controller recognizes
Fast Interrupts before the core does.
Fast Interrupt Handling
A Fast Interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIM
n
register to the appropriate vector number
3. Setting the FIVAL
n
and FIVAH
n
registers with the address of the code for the
Fast Interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector
address from the appropriate FIVAL
n
and FIVAH
n
registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its Fast Interrupt handling.
Table 5-1 Interrupt Mask Bit Definition
SR[9]
SR[8]
Exceptions Permitted
Exceptions Masked
0
0
Priorities 0, 1, 2, 3
None
0
1
Priorities 1, 2, 3
Priority 0
1
0
Priorities 2, 3
Priorities 0, 1
1
1
Priority 3
Priorities 0, 1, 2
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相關(guān)代理商/技術(shù)參數(shù) |
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| 56F8014_07 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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