參數(shù)資料
型號(hào): 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 7/124頁(yè)
文件大?。?/td> 1878K
代理商: 56F8014
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Award-Winning Development Environment
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
7
PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100%
modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction
Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable
Reluctance Motors), and stepper motors. The PWM incorporates fault protection and cycle-by-cycle
current limiting with sufficient output drive capability to directly drive standard optoisolators. A
“smoke-inhibit”, write-once protection feature for key parameters is also included. A patented PWM
waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes
interrupt controls to permit integral reload rates to be programmable from 1/2 (center-aligned mode only)
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converter
(ADC) through Quad Timer, Channels 2 and 3.
This Digital Signal Controller also provides a full set of standard programmable peripherals that include
one Serial Communications Interface (SCI), one Serial Peripheral Interface (SPI), one Quad Timer, and
one Inter-Integrated Circuit (I
2
C) interface. Any of these interfaces can also be used as General Purpose
Input/Outputs (GPIOs).
1.3 Award-Winning Development Environment
Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8014’s architecture is shown in
Figure 1-1
,
Figure 1-2
, and
Figure 1-3
.
Figure 1-1
illustrates
how the 56800E system buses communicate with internal memories and the IPBus Bridge.
Table 1-1
lists
the internal buses in the 56800E architecture and provides a brief description of their function.
Figure 1-2
and
Figure 1-3
show the peripherals and control blocks connected to the IPBus Bridge. The figures do not
show the on-board regulator and power and ground signals. They also do not show the multiplexing
between peripherals or the dedicated GPIOs. Please see
Part 2 Signal/Connection Descriptions
to see
which signals are multiplexed with those of other peripherals.
1.4.1
Figure 1-3
shows the over/under voltage connections from the ADC to the PWM and the connections to
the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner to the
over/under voltage control signals. See the
56F8000 Peripheral Reference Manual
for additional
information.
PWM, TMR and ADC Connections
The PWM_reload_sync output can be connected to the TMR channel 3 input and the TMR channels 2 and
3 outputs are connected to the ADC sync inputs. TMR channel 3 output is connected to SYNCO and TMR
channel 2 is connected to SYNC1. These are controlled by bits in the SIM Control Register; see
Section
6.3.1
.
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