
Register Descriptions
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
67
6.3.2.2
Software Reset (SWR)—Bit 5
When set, this bit indicates that the previous system reset occurred as a result of a software reset (written
1 to SW RST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also
occurred.
6.3.2.3
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
(COP) timer. It will not be set if an external or POR reset also occurred. If COPR is set as code starts
executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.
COP Reset (COPR)—Bit 4
6.3.2.4
When set, this bit indicates that the previous system reset was caused by an external reset. It will only be
set if the external reset pin was asserted or remained asserted after the Power-On Reset deasserted.
External Reset (EXTR)—Bit 3
6.3.2.5
This bit is set during a Power-On Reset.
Power-On Reset (POR)—Bit 2
6.3.2.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 1–0
6.3.3
SIM Software Control Registers (SIM_SWC0, SIM_SWC1,
SIM_SWC2, and SIM_SWC3)
Only SIM_SWC0 is shown in this section. SIM_SWC1, SIM_SWC2, and SIM_SWC3 are identical in
functionality.
Figure 6-4 SIM Software Control Register 0 (SIM_SWC0)
6.3.3.1
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
Software Control Data 0 (FIELD)—Bits 15–0
6.3.4
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F2.
Most Significant Half of JTAG ID (SIM_MSHID)
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
Software Control Data 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0