參數(shù)資料
型號(hào): 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 18/124頁(yè)
文件大?。?/td> 1878K
代理商: 56F8014
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56F8014 Technical Data, Rev. 3
18
Freescale Semiconductor
Preliminary
GPIOB5
(T1)
(FAULT3)
3
Input/
Output
Input/
Output
Output
Input, pulled
high
internally
Port B GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
T1
— Timer, Channel 1
FAULT3
— This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
After reset, the default state is GPIOB5. The peripheral functionality
is controlled via the SIM. See
Section 6.3.8
.
TCK
(GPIOD2)
15
Input
Input/
Output
Input, pulled
high
internally
Test Clock Input
— This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-up resistor. A Schmitt
trigger input is used for noise immunity.
Port D GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TCK.
TMS
(GPIOD3)
30
Input
Input/
Output
Input, pulled
high
internally
Test Mode Select Input
— This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Port D GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TMS.
TDI
(GPIOD0)
29
Input
Input/
Output
Input, pulled
high
internally
Test Data Input
— This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
Port D GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDI.
Return to
Table 2-2
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
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