參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 32/124頁
文件大小: 1878K
代理商: 56F8014
56F8014 Technical Data, Rev. 3
32
Freescale Semiconductor
Preliminary
4.6 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-6
summarizes base addresses for the set of peripherals on the 56F8014 device. Peripherals are
listed in order of the base address.
The following tables
list all of the peripheral registers required to control or access the peripherals.
Table 4-6 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
Timer
PWM
ITCN
ADC
SCI
SPI
TMR
n
PWM
ITCN
ADC
SCI
SPI
I2C
X:$00 F000
X:$00 F040
X:$00 F060
X:$00 F080
X:$00 F0B0
X:$00 F0C0
X:$00 F0D0
4-7
4-8
4-9
4-10
4-11
4-12
4-13
I
2
C
COP
CLK, PLL, OSC, TEST
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SIM
Power Supervisor
FM
COP
OCCS
GPIOA
GPIOB
GPIOC
GPIOD
SIM
PS
FM
X:$00 F0E0
X:$00 F0F0
X:$00 F100
X:$00 F110
X:$00 F120
X:$00 F130
X:$00 F140
X:$00 F160
X:$00 F400
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
Table 4-7 Quad Timer Registers Address Map
(TMR_BASE = $00 F000)
Register Acronym
Address Offset
Register Description
TMR0_COMP1
$0
Compare Register 1
TMR0_COMP2
$1
Compare Register 2
TMR0_CAPT
$2
Capture Register
TMR0_LOAD
$3
Load Register
TMR0_HOLD
$4
Hold Register
TMR0_CNTR
$5
Counter Register
TMR0_CTRL
$6
Control Register
TMR0_SCTRL
$7
Status and Control Register
TMR0_CMPLD1
$8
Comparator Load Register 1
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