參數資料
型號： 56F8014
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數字信號控制器
文件頁數： 117/124頁
文件大?。?/td> 1878K
代理商： 56F8014
Electrical Design Considerations
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
117
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation of the 56F8014:
Provide a low-impedance path from the board power supply to each V
DD
pin on the 56F8014 and from the
board ground to each V
SS
(GND) pin
The minimum bypass requirement is to place 0.01–0.1
μ
F capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the V
DD
/V
SS
pairs, including V
DDA
/V
SSA.
Ceramic and tantalum capacitors tend to provide better
tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
DD
and V
SS
(GND)
pins are as short as possible
Bypass the V
DD
and V
SS
with approximately 100
μ
F, plus the number of 0.1
μ
F ceramic capacitors
PCB trace lengths should be minimal for high-frequency signals
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V
DD
and V
SS
circuits.
Take special care to minimize noise levels on the V
REF
, V
DDA
and V
SSA
pins
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
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