參數資料
型號: 56F8014
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數字信號控制器
文件頁數: 47/124頁
文件大?。?/td> 1878K
代理商: 56F8014
Register Descriptions
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
47
5.6.1
Interrupt Priority Register 0 (IPR0)
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities
0 through 2 and is disabled by default.
LVI IPL—Bits 15–14
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.1.2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 13–10
5.6.1.3
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)— Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)— Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
LVI IPL
0
0
0
0
RX_REG IPL
TX_REG IPL
TRBUF IPL
BKPT_U IPL
STPCNT IPL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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