參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 79/124頁
文件大?。?/td> 1878K
代理商: 56F8014
Resets
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
79
Figure 6-15
provides a graphic illustration of the details in
Table 6-4
. Note that the POR_Delay blocks
use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this
phase of reset.
Figure 6-15 Sources of RESET Functional Diagram (Test modes not included)
POR resets are extended 64 MSTR_OSC clocks to stabilize the power supply. All resets are subsequently
extended for an additional 32 MSTR_OSC clocks and 64 system clocks as the various internal reset
controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset
from when power comes on to when code is running is 28
μ
S. An external reset generation chip may also
be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge
of the system clock.
EXTENDED_POR
JTAG
Memory
Subsystem
Peripherals
56800E
CORE_RST
Delay 32
sys clocks
OCCS
CLKGEN_RST
PERIP_RST
Delay 32
sys clocks
pulse shaper
pulse shaper
SW Reset
pulse shaper
Delay 32
MSTR_OSC
Clocks
pulse shaper
Delay 64
MSTR_OSC
Clocks
POR
Power-On
Reset
(active
low)
External
RESET IN
(active
low)
COP
(active
low)
RESET
Delay blocks assert immediately and
deassert only after the programmed
number of clock cycles.
COMBINED_RST
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