參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 16/124頁
文件大?。?/td> 1878K
代理商: 56F8014
56F8014 Technical Data, Rev. 3
16
Freescale Semiconductor
Preliminary
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
V
DD_IO
25
Supply
Supply
I/O Power
— This pin supplies 3.3V power to the chip I/O interface.
V
SS_IO
14
Supply
Supply
V
SS
— These pins provide ground for chip logic and I/O drivers.
V
SS_IO
26
V
DDA
8
Supply
Supply
ADC Power
— This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
V
SSA
9
Supply
Supply
ADC Analog Ground
— This pin supplies an analog ground to the
ADC modules.
V
CAP
24
Supply
Supply
V
CAP
Connect this pin to a 4.4
μ
F or greater bypass capacitor in
order to bypass the core voltage regulator, required for proper chip
operation. See
Section 10.2.1
.
GPIOB6
(RXD)
(SDA
1
)
(CLKIN)
32
Input/
Output
Input
Input/
Output
Input
Input, pulled
high
internally
Port B GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
Receive Data
— SCI receive data input.
Serial Data
— This pin serves as the I
2
C serial data line.
Clock Input
— This pin serves as an optional external clock input.
After reset, the default state is GPIOB6. The peripheral functionality
is controlled via the SIM (See
Section 6.3.8
) and the CLKMODE bit
of the OCCS Oscillator Control Register.
1.
This signal is also brought out on the GPIOB1 pin.
Return to
Table 2-2
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