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參數(shù)資料
| 型號(hào)： | 56F8014 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號(hào)控制器 |
| 文件頁(yè)數(shù)： | 82/124頁(yè) |
| 文件大小： | 1878K |
| 代理商： | 56F8014 |
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56F8014 Technical Data, Rev. 3
82
Freescale Semiconductor
Preliminary
Part 7 Security Features
The 56F8014 offers security features intended to prevent unauthorized users from reading the contents of
the Flash Memory (FM) array. The 56F8014’s Flash security consists of several hardware interlocks that
prevent unauthorized users from gaining access to the Flash array.
Note, however, that part of the security must lie with the user’s code. An extreme example would be user’s
code that includes a subroutine to read and transfer the contents of the internal program to SCI, SPI or
another peripheral, as this code would defeat the purpose of security. At the same time, the user may also
wish to put a “backdoor” in his program. As an example, the user downloads a security key through the
SCI, allowing access to a programming routine that updates parameters stored in another section of the
Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8014 can be secured by
programming the security bytes located in the FM configuration field, which are located at the last 9 words
of Program Flash. These non-volatile bytes will keep the part secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to
the Flash Memory chapter in the
56F8000 Peripheral Reference Manual
for the state of the security
bytes and the resulting state of security. When Flash security mode is enabled in accordance with the
method described in the Flash Memory module chapter, the 56F8014 will disable the core EOnCE debug
capabilities. Normal program execution is otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
The 56F8014 has several operating functional and debug modes. Effective Flash security must address
operating mode selection and anticipate modes in which the on-chip Flash can be read without explicit user
permission.
7.2.1
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the
EOnCE port functionality is mapped. When the 56F8014 boots, the chip-level JTAG TAP (Test Access
Port) is active and provides the chip’s boundary scan capability and access to the ID register, but proper
implementation of Flash security will block any attempt to access the internal Flash memory via the
EOnCE port when security is enabled.
Disabling EOnCE Access
7.2.2
If a user inadvertently enables security on the 56F8014, the only lockout recovery mechanism is the
complete erasure of the internal Flash contents, including the configuration field, and thus disables security
(the protection register is cleared). This does not compromise security, as the entire contents of the user’s
secured code stored in Flash are erased before security is disabled on the 56F8014 on the next reset or
power-up sequence.
Flash Lockout Recovery Using JTAG
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相關(guān)代理商/技術(shù)參數(shù) |
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| 56F8014_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| 56F8014_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| 56F801E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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| 56F802 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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