參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 70/124頁
文件大?。?/td> 1878K
代理商: 56F8014
56F8014 Technical Data, Rev. 3
70
Freescale Semiconductor
Preliminary
6.3.7.7
Selects clock to be muxed out on the CLKO pin.
Clockout Select (CLKOSEL)—Bits 4–0
00000 = Reserved for factory test—Continuous system clock
01001 = Reserved for factory test—OCCS MSTR OSC clock
01011 = Reserved for factory test—ADC clock
01100 = Reserved for factory test—JTAG TCLK
01101 = Reserved for factory test—Continuous peripheral clock
01110 = Reserved for factory test—Continuous inverted peripheral clock
01111 = Reserved for factory test—Continuous high-speed peripheral clock
6.3.8
All of the peripheral pins on the 56F8014 share their Input/Output (I/O) with GPIO ports. In order to select
peripheral or GPIO control, program the GPIO
x
_PEREN register. In some cases, there are two possible
peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS
register is used to determine which peripheral has control.
SIM GPIO Peripheral Select Register (SIM_GPS)
As shown in
Figure 6-9
, the GPIO Peripheral Enable Register (PEREN) has the final control over which
pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when
PEREN = 1.
Figure 6-9 Overall Control of Pads Using SIM_GPS Control
GPIOB_PEREN Register
GPIO Controlled
I/O
Pad Control
SIM_GPS Register
Quad Timer Controlled
SCI Controlled
0
1
0
1
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