參數資料
型號: 56F8014
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數字信號控制器
文件頁數: 91/124頁
文件大小: 1878K
代理商: 56F8014
56F8014 Information
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
91
Part 9 Joint Test Action Group (JTAG)
9.1 56F8014 Information
Please contact your
Freescale
sales representative or authorized distributor for device/package-specific
BSDL information.
The TRST pin is not available in this package. The pin is tied to V
DD
in the package.
The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high
for five rising edges of TCK, as described in the
56F8000 Peripheral User Manual
.
Part 10 Specifications
10.1 General Characteristics
The 56F8014 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The
term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
±
10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in
Table 10-1
are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40oC to
105oC ambient temperature over the following supply ranges:
V
SS
= V
SS
A = 0V, V
DD
= V
DDA
= 3.0–3.6V, CL <
50pF, f
OP
= 32MHz
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid
application
of any
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
voltages
higher
than
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