In-System Programming (ISP) of Actel’s Low-Power Flash Devices Using FlashPro3
v1.1
16- 9
Board-Level Considerations
A bypass capacitor is required from VPUMP to GND for all low-power flash devices during
programming. This bypass capacitor protects the devices from voltage spikes that may occur on the
VPUMP supplies during the erase and programming cycles. Refer to Pin Descriptions for specific recommendations. For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are
to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as
possible. The bypass capacitor must be placed within 2.5 cm of the device pins.
Troubleshooting Signal Integrity
Symptoms of a Signal Integrity Problem
A signal integrity problem can manifest itself in many ways. The problem may show up as extra or
dropped bits during serial communication, changing the meaning of the communication. There is a
normal variation of threshold voltage and frequency response between parts even from the same
lot. Because of this, the effects of signal integrity may not always affect different devices on the
same board in the same way. Sometimes, replacing a device appears to make signal integrity
problems go away, but this is just masking the problem. Different parts on identical boards will
exhibit the same problem sooner or later. It is important to fix signal integrity problems early.
Unless the signal integrity problems are severe enough to completely block all communication
between the device and the programmer, they may show up as subtle problems. Some of the
FlashPro3 exit codes that are caused by signal integrity problems are listed below. Signal integrity
problems are not the only possible cause of these errors, but this list is intended to show where
problems can occur. FlashPro3 allows TCK to be lowered from 24 MHz down to 1 MHz to allow you
to address some signal integrity problems that may occur with impedance mismatching at higher
frequencies.
Chain Integrity Test Error or Analyze Chain Failure
Normally, the FlashPro3 Analyze Chain command expects to see 0x2 on the TDO pin. If the
command reports reading 0x0 or 0x3, it is seeing the TDO pin stuck at 0 or 1. The only time the TDO
pin comes out of tristate is when the JTAG TAP state machine is in the Shift-IR or Shift-DR state. If
Figure 16-6 Board Layout and Programming Header Top View
VCC
VCCI
VJTAG
GND
TCK
TDO
TMS
VPUMP
TDI
TRST
1 TCK
2 GND
3 TDO
4 NC
5 TMS
6 VJTAG
7 VPUMP
8 TRST
9 TDI
10 GND
Low-Power Flash Device
VCC from the target board
VJTAG from the target board
VCCI from the target board
Polarizing Notch