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參數(shù)資料
| 型號(hào)： | AD5522JSVDZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 38/64頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PMU QUAD 16BIT DAC 80-TQFP |
| 產(chǎn)品變化通告： | Improve FI ac crosstalk |
| 設(shè)計(jì)資源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 每引腳參數(shù)測(cè)量單元（PPMU） |
| 應(yīng)用： | 自動(dòng)測(cè)試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（12x12） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 798 (CN2011-ZH PDF) |
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Data Sheet
AD5522
Rev. E | Page 43 of 64
Because there is only one calibration engine shared among four
channels, the task of calculating X2 values must be done sequentially,
so that the length of the BUSY pulse varies according to the
number of channels being updated. Following any register
update, including multiple channel updates, subsequent writes
should either be timed or should wait until BUSY returns high
(see Figure 56). If subsequent writes are presented before the
calibration engine completes the first stage of the last Channel X2
calculation, data may be lost.
Table 17. BUSY Pulse Widths
Action
BUSY Pulse Width1
Loading Data to System Control
Register, or Readback2
0.27 s maximum
Loading X1 to 1 PMU DAC Channel
1.65 s maximum
Loading X1 to 2 PMU DAC Channels
2.3 s maximum
Loading X1 to 3 PMU DAC Channels
2.95 s maximum
Loading X1 to 4 PMU DAC Channels
3.6 s maximum
1
BUSY pulse width = ((number of channels + 1) × 650 ns) + 350 ns.
2
Refer to Table 18 for details of PMU register effect on BUSY pulse width.
BUSY also goes low during a power-on reset and when a falling
edge is detected on the RESET pin.
WRITE 1
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
~650ns
650ns
CALIBRATION ENGINE TIME
FOR EXAMPLE,
WRITE TO 3 FIN
DAC REGISTERS
350ns
WRITE 2
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
06197-
035
Figure 56. Multiple Writes to DAC X1 Registers
Writing data to the system control register, some PMU control
bits (see Table 18), the M register, and the C register do not
involve the digital calibration engine, thus speeding up
configuration of the device on power-on. However, care should
be taken not to issue these commands while BUSY is low, as
previously described.
Table 18. BUSY Pulse Widths for PMU Register Updates
PMU Register Update (See
Maximum BUSY Low Time per Channel Update
Bit
Bit Name
One
Channel
Two
Channels
Three
Channels
Four
Channels
21
CH EN
270 ns
20, 19
FORCE1, FORCE0 (depends on mode change)
Transition From
Transition To
High-Z FOHx current (11)
Force current (01)
270 ns
High-Z FOHx current (11)
Force voltage (00)
1.65 s
2.3 s
2.95 s
3.6 s
High-Z FOHx current (11)
High-Z FOHx voltage (10)
1.65 s
2.3 us
2.95 us
3.6 s
Force current (01)
High-Z FOHx current (11)
270 ns
Force current (01)
High-Z FOHx voltage (10)
1.65 s
2.3 s
2.95 s
3.6 s
Force current (01)
Force voltage (00)
1.65 s
2.3 s
2.95 s
3.6 s
High-Z FOHx voltage (10)
Force voltage (00)
270 ns
High-Z FOHx voltage (10)
Force current (01)
1.65 s
2.3 s
2.95 s
3.6 s
High-Z FOHx voltage (10)
High-Z FOHx current (11)
1.65 s
2.3 s
2.95 s
3.6 s
Force voltage (00)
High-Z FOHx voltage (10)
270 ns
Force voltage (00)
High-Z FOHx current (11)
1.65 s
2.3 s
2.95 s
3.6 s
Force voltage (00)
Force current (01)
1.65 s
2.3 s
2.95 s
3.6 s
17, 16, 15
C2 to C0; current range selection (any range change)
1.65 s
2.3 s
2.95 s
3.6 s
14, 13
MEASx (measure mode selection)
270 ns
12
FIN
270 ns
11
SFO
270 ns
10
SS0
270 ns
9
CL
270 ns
8
CPOLH
270 ns
7
Compare V/I
1.65 s
2.3 s
2.95 s
3.6 s
6
Clear
270 ns
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