參數(shù)資料
型號: AD5522JSVDZ
廠商: Analog Devices Inc
文件頁數(shù): 45/64頁
文件大小: 0K
描述: IC PMU QUAD 16BIT DAC 80-TQFP
產(chǎn)品變化通告: Improve FI ac crosstalk
設(shè)計資源: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
標準包裝: 1
類型: 每引腳參數(shù)測量單元(PPMU)
應(yīng)用: 自動測試設(shè)備
安裝類型: 表面貼裝
封裝/外殼: 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 80-TQFP(12x12)
包裝: 托盤
產(chǎn)品目錄頁面: 798 (CN2011-ZH PDF)
Data Sheet
AD5522
Rev. E | Page 5 of 64
DUTGND
GUARD0
CPOL0/SCLK
CPOH0/SDI
GUARDIN0/
DUTGND0
DUT
SYS_FORCE
SYS_SENSE
CGALM
CPOL2/CPO0
CPOL1/SYNC
CPOH1/SDO
CPOH2/CPO1
TMPALM
CLAMP AND
GUARD
ALARM
TEMP
SENSOR
TO
MEASOUT
MUX
MEASVH3
FOH3
EXTMEASIH3
EXTMEASIL3
CH1
CH0
CH2
CH3
FOH2
EXTFOH2
EXTMEASIH2
EXTMEASIL2
MEASVH2
GUARD2
MEASVH1
EXTMEASIL1
FOH1
EXTFOH1
CFF1
CFF3
CFF2
EXTMEASIH1
GUARD1
GUARDIN1/DUTGND1
MEASOUT1
CCOMP1
CCOMP2
MEASOUT2
AGND
DUTGND
16
MEASVH0
CPOL3/
CPO2
CPOH3/
CPO3
SPI/
LVDS
EXTERNAL
RSENSE
(CURRENTS
UP TO ±80mA)
EXTMEASIH0
EXTMEASIL0
FOH0
EXTFOH0
CFF0
FIN
CLH
CLL
AVSS
AVDD
AGND
+
MEASOUT0
DGND
CPH
COMPARATOR
CCOMP0
CPL
+
+
+
RSENSE
+
16
VREF
DVCC
16
X1 REG
C REG
M REG
16
16-BIT
FIN DAC
×5 OR ×10
×2
×1
AGND
REFGND
16-BIT
CLH DAC
MEASOUT
MUX AND GAIN
×1/×0.2
X1 REG
C REG
M REG
X1 REG
C REG
M REG
×2
16
X1 REG
C REG
M REG
×6
OFFSET DAC
FORCE
AMPLIFIER
16-BIT
CLL DAC
16-BIT
CPH DAC
16-BIT
CPL DAC
SW1
SW2
SW3
SW4
SW6
SW9
SW8
SW5
SW10
SW11
MEASURE
VOLTAGE
IN-AMP
MEASURE
CURRENT
IN-AMP
TEMP
SENSOR
SW12
X1 REG
C REG
M REG
×6
X2 REG
×6
X2 REG
×6
×2
AGND
EN
GUARD AMP
SW13
SW14
AGND
10k
SW15
SW16
DUTGND
VMID TO
CENTER
I RANGE
AGND
10k
AGND
10k
+
GUARDIN2/DUTGND2
EXTFOH3
16
GUARDIN3/
DUTGND3
GUARD3
DUT
EXTERNAL
RSENSE
(CURRENTS
UP TO ±80mA)
FIN
CLH
CLL
AGND
+
MEASOUT3
CPH
COMPARATOR
CPL
INTERNAL RANGE
SELECT
(±5A, ±20A, ±200A, ±2mA)
INTERNAL RANGE
SELECT
(±5A, ±20A, ±200A, ±2mA)
+
+
+
RSENSE
+
16
CCOMP3
16
X1 REG
C REG
M REG
16
16-BIT
FIN DAC
x5 or x10
×2
x1
AGND
16-BIT
CLH DAC
MEASOUT
MUX AND GAIN
x1/x0.2
X1 REG
C REG
M REG
X1 REG
C REG
M REG
×2
16
X1 REG
C REG
M REG
×6
OFFSET DAC
FORCE
AMPLIFIER
16-BIT
CLL DAC
16-BIT
CPH DAC
16-BIT
CPL DAC
SW1
SW2
SW3
SW4
SW6
SW5
SW9
SW8
SW10
SW11
MEASURE
VOLTAGE
IN-AMP
MEASURE
CURRENT
IN-AMP
TEMP
SENSOR
SW12
C REG
M REG
×6
X2 REG
×6
X2 REG
×6
×2
EN
GUARD AMP
SW13
SW14
SW15
SW15a
SW16
DUTGND
VMID TO
CENTER
I RANGE
+
06197-
002
MUX
SCLK
SYNC
SDI
SDO
SERIAL
INTERFACE
RESET
BUSY
16
POWER-ON
RESET
LOAD
16
16-BIT
OFFSET
DAC
TO ALL DAC
OUTPUT
AMPLIFIERS
X1 REG
AGND
SW7
4k
2k
MEASVH
(Hi-Z)
AGND
MEASVH
(Hi-Z)
4k
SW7
4k
Figure 2. Detailed Block Diagram
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