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| 型號： | AD5522JSVDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 43/64頁 |
| 文件大小： | 0K |
| 描述： | IC PMU QUAD 16BIT DAC 80-TQFP |
| 產品變化通告： | Improve FI ac crosstalk |
| 設計資源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) |
| 標準包裝： | 1 |
| 類型： | 每引腳參數測量單元（PPMU） |
| 應用： | 自動測試設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應商設備封裝： | 80-TQFP（12x12） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 798 (CN2011-ZH PDF) |
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AD5522
Data Sheet
Rev. E | Page 48 of 64
WRITE PMU REGISTER
To address PMU functions, set the MODE1 and MODE0 bits
to 0. This setting selects the PMU register (see Table 19 and
Table 20). The AD5522 has very flexible addressing, which
allows writing of data to a single PMU channel, any
combination of PMU channels, or all PMU channels. This
functionality enables multipin broadcasting to similar pins on
a DUT. Bit 27 to Bit 24 select the PMU or group of PMUs that
is addressed.
Table 24. PMU Register Bits—Bit B28 to Bit B15
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B181
B17
B16
B15
RD/WR
PMU3
PMU2
PMU1
PMU0
MODE1
MODE0
CH EN
FORCE1
FORCE0
0
C2
C1
C0
1
Bit B18 is reserved.
Table 25. PMU Register Bits—Bit B14 to Bit B0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B51
MEAS1
MEAS0
FIN
SF0
SS0
CL
CPOLH
Compare V/I
Clear
0
1
Bit B5 to Bit B0 are unused data bits.
Table 26. PMU Register Functions
Bit
Bit Name
Description
28 (MSB)
RD/WR
When low, a write to the selected register takes place; setting the RD/WR bit high initiates a readback sequence
of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits.
27
PMU3
Bit PMU3 to Bit PMU0 address each PMU channel in the device. These bits allow control of an individual PMU
channel or any combination of channels, in addition to multichannel programming (see Table 20).
26
PMU2
25
PMU1
24
PMU0
23
MODE1
Set the MODE1 and MODE0 bits to 0 to access the PMU register selected by the PMU3 to PMU0 bits (Bit 27 to
Bit 24).
22
MODE0
PMU Register-Specific Bits
21
CH EN
Channel enable. Set high to enable the selected channel or group of channels; set low to disable the selected
channel or channels. When disabled, SW2 is closed and SW5 is open (outputs are high-Z). The measure mode is
determined by the MEAS1 and MEAS0 bits at all times and is not affected by the CH EN bit. The guard amplifier
and the comparators are not affected by this bit.
20
FORCE1
The FORCE1 and FORCE0 bits set the force function for each PMU channel (in association with the PMUx bits).
All combinations of forcing and measuring (using the MEAS1 and MEAS0 bits) are available. The high-Z (voltage
and current) modes allow the user to optimize glitch response during mode changes. While in high-Z voltage or
current mode, with the PMU high-Z, new X1 codes loaded to the FIN DAC register and to the clamp DAC register
are calibrated, stored in the X2 register, and loaded directly to the DAC outputs.
19
FORCE0
FORCE1
FORCE0
Action
0
FV and current clamp (if clamp is enabled).
0
1
FI and voltage clamp (if clamp is enabled).
1
0
High-Z FOHx voltage (preload FIN DAC and clamp DAC).
1
High-Z FOHx current (preload FIN DAC and clamp DAC).
18
Reserved
0
17
C2
Bit C2 to Bit C0 specify the required current range. High-Z FV/FI commands ignore the current range address
bits (C2, C1, and C0); therefore, these bit combinations cannot be used to enable or disable the force function
for a PMU channel.
16
C1
15
C0
C2
C1
C0
Selected Current Range
0
±5 A current range.
0
1
±20 A current range.
0
1
0
±200 A current range.
0
1
±2 mA current range (default).
1
0
±external current range.
1
0
1
Disable the always on mode for the external current range buffer1.
1
0
Enable the always on mode for the external current range buffer2.
1
Reserved.
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