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參數(shù)資料
| 型號(hào)： | AD5522JSVDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PMU QUAD 16BIT DAC 80-TQFP |
| 產(chǎn)品變化通告： | Improve FI ac crosstalk |
| 設(shè)計(jì)資源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 每引腳參數(shù)測(cè)量單元（PPMU） |
| 應(yīng)用： | 自動(dòng)測(cè)試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（12x12） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 798 (CN2011-ZH PDF) |
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AD5522
Data Sheet
Rev. E | Page 44 of 64
REGISTER UPDATE RATES
The value of the X2 register is calculated each time the user writes
new data to the corresponding X1 register and for some PMU
register updates. The calculation is performed in a three-stage
process. The first two stages take approximately 650 ns each, and
the third stage takes approximately 350 ns. When the write to the X1
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user is
free to write to another X1 register, provided that the write
operation does not finish (SYNC returns high) until after the
first-stage calculation is complete, that is, 650 ns after the
completion of the first write operation.
WRITE 1
WRITE 2
WRITE 3
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
~650ns
650ns
CALIBRATION ENGINE TIME
350ns
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
06197-
036
Figure 57. Multiple Single-Channel Writes Engaging the Calibration Engine
REGISTER SELECTION
The serial word assignment consists of 29 bits. Bit 28 to Bit 22
are common to all registers, whether writing to or reading from
the device. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address
each PMU channel (or associated DAC register). When the
PMU3 to PMU0 bits are all 0s, the system control register is
addressed.
The mode bits, MODE0 and MODE1, address the different sets
of DAC registers and the PMU register.
Table 19. Mode Bits
B23
MODE1
B22
MODE0
Action
0
Write to the system control register or
the PMU register
0
1
Write to the DAC gain (M) register
1
0
Write to the DAC offset (C) register
1
Write to the DAC input data (X1) register
Readback Control, RD/WR
Setting the RD/WR bit (Bit 28) high initiates a readback
sequence of the PMU, alarm status, comparator status, system
control, or DAC register, as determined by the address bits.
PMU Address Bits: PMU3, PMU2, PMU1, PMU0
The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each
PMU channel on chip. These bits allow individual control of
each PMU channel or any combination of channels, in addition
to multichannel programming. PMU bits also allow access to
write registers such as the system control register and the DAC
registers, in addition to reading from all the registers (see Table 20).
NOP (No Operation)
If an NOP (no operation) command is loaded, no change is
made to the DAC or PMU registers. This code is useful when
performing a readback of a register within the device (via the
SDO pin) where a change of DAC code or PMU function may
not be required.
Reserved Commands
Any bit combination that is not described in the register address
tables for the PMU, DAC, and system control registers indicates
a reserved command. These commands are unassigned and are
reserved for factory use. To ensure correct operation of the
device, do not use reserved commands.
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