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參數(shù)資料
| 型號(hào)： | AD5522JSVDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PMU QUAD 16BIT DAC 80-TQFP |
| 產(chǎn)品變化通告： | Improve FI ac crosstalk |
| 設(shè)計(jì)資源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 每引腳參數(shù)測量單元（PPMU） |
| 應(yīng)用： | 自動(dòng)測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（12x12） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 798 (CN2011-ZH PDF) |
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Data Sheet
AD5522
Rev. E | Page 51 of 64
DAC Addressing
For the FIN and comparator (CPH and CPL) DACs, there is a
set of X1, M, and C registers for each current range, and one set
for the voltage range; for the clamp DACs (CLL and CLH),
there are only two sets of X1, M, and C registers.
When calibrating the device, the M and C registers allow volatile
storage of gain and offset coefficients. Calculation of the corres-
ponding DAC X2 register occurs only when the X1 data is loaded
(no internal calculation occurs on M or C updates).
There is one offset DAC for all four channels in the device that
is addressed using the PMUx bits. The offset DAC has only an
input register associated with it; no M or C registers are asso-
ciated with this DAC. When writing to the offset DAC, set the
MODE1 and MODE0 bits high to address the DAC input
register (X1).
The same address table is also used for readback of a particular
DAC address.
Note that CLL is clamp level low and CLH is clamp level high.
When forcing a voltage, the current clamps are engaged;
therefore, both the CLL current ranges register set and the
CLH current ranges register set are loaded to the clamp DACs.
When forcing a current, the voltage clamps are engaged;
therefore, both the CLL voltage range register set and the
CLH voltage range register set are loaded to the clamp DACs.
All codes not explicitly referenced Table 29 are reserved and
should not be used.
Table 29. DAC Register Addressing
A5
A4
A3
A2
A1
A0
MODE1
MODE0
Register Set
Addressed Register
0
1
N/A
Offset DAC X
0
1
0
1
±5 A current range
FIN M
1
0
FIN C
1
FIN X1
0
1
0
1
0
1
±20 A current range
FIN M
1
0
FIN C
1
FIN X1
0
1
0
1
0
1
±200 A current range
FIN M
1
0
FIN C
1
FIN X1
0
1
0
1
0
1
±2 mA current range
FIN M
1
0
FIN C
1
FIN X1
0
1
0
1
±external current range
FIN M
1
0
FIN C
1
FIN X1
0
1
0
1
0
1
Voltage range
FIN M
1
0
FIN C
1
FIN X1
0
1
0
1
0
1
Current ranges
CLL M
1
0
CLL C
1
CLL X11
0
1
0
1
0
1
0
1
Voltage range
CLL M
1
0
CLL C
1
CLL X1
0
1
0
1
Current ranges
CLH M
1
0
CLH C
1
CLH X12
0
1
0
1
0
1
Voltage range
CLH M
1
0
CLH C
1
CLH X1
1
0
1
±5 A current range
CPL M
1
0
CPL C
1
CPL X1
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