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| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 22 of 76
Phase Detector Gain Matching
Although the fine and coarse phase detectors use different means
to make a timing measurement, it is essential that both have
equivalent phase gain. Without proper gain matching, the
closed-loop dynamics of the system cannot be properly
controlled. Hence, the goal is to make PhaseGainCPD =
PhaseGainFPD.
This leads to
Gain
FPFD
PDG
f PDS
S
_
)
10
2
(
)
2
(
7
10
6
×
=
+
which simplifies to
S
PDS
f
Gain
FPFD
PDG
_
)
10
16
(
2
7
×
=
Typically, FPFD_Gain is established first, and then PDG and
PDS are calculated. The proper choice for PDS is given by
×
=
S
f
Gain
FPFD
PDS
2
_
10
log
round
7
2
The final value of PDS must satisfy 0 ≤ PDS ≤ 7. The proper
choice for PDG is calculated using the following equation:
=
S
PDS
f
Gain
FPFD
PDG
4
7
2
_
10
round
The final value of PDG must satisfy 0 ≤ PDG ≤ 63. For example,
let fS = 700 MHz and FPFD_Gain = 200; then PDS = 1 and
PDG = 23.
Note that the AD9549 evaluation software calculates register
values that have the phase detector gains already matched.
Phase Detector Pin Connections
There are three pins associated with the phase detector that
must be connected to external components. Figure 27 shows the
recommended component values and their connections.
06744-
027
10F
0.1F
PFD_VRT
PFD_RSET
PFD_VRB
AD9549
0.1F
4.99k
20
21
22
Figure 27. Phase Detector Pin Connections
DIGITAL LOOP FILTER COEFFICIENTS
To provide the desired flexibility, the loop filter has been
designed with three programmable coefficients (α, β, and γ).
The coefficients, along with P (where P = 2PIO), completely
define the response of the filter, which is given by
+
+
+
=
)
1
(
)
2
(
)
1
(
)
(
2
γ
e
γ
e
γ
β
e
α
ω
H
jω
ω
j
jω
LoopFilter
To evaluate the response in terms of absolute frequency, substitute
S
f
Pf
ω
π
= 2
where P is the divide ratio of the P-divider, fS is the DAC sample
rate, and f is the frequency at which the function is to be evaluated.
The loop filter coefficients are determined by the AD9549
evaluation software according to three parameters:
Φ is the desired closed-loop phase margin (0 < Φ< π/2 rad).
fLOOP is the desired open-loop bandwidth (Hz).
fDDS is the desired output frequency of the DDS (Hz).
Note that fDDS can also be expressed as fDDS = fR(S/R).
The three coefficients are calculated according to parameters
via the following equations:
)
tan(
4
Φ
Pf
β
C
π
=
β
Φ
F
γ
)
(
2
1
=
β
Φ
F
f
Gain
FPFD
α
C
DDS
)
(
_
10
2
7
38
π
=
where:
)
sin(
1
)
(
Φ
F
+
=
S
LOOP
C
f
f =
FPFD_Gain is the value of the gain scale factor for the fine
phase detector as programmed into the I/O register map.
Note that the range of loop filter coefficients is limited as follows:
0 < α < 223 (~8.39 × 106)
0.125 < β < 0
0.125 < γ < 0
The preceding constraints on β and γ constrain the closed-loop
phase margin such that both β and γ assume negative values.
Even though β and γ are limited to negative quantities, the values as
programmed are positive. The negative sign is assumed internally.
Note that the closed-loop phase margin is limited to the range
of 0° < Φ < 90° because β and γ are negative.
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|---|---|
| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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