參數(shù)資料
型號: AD9549ABCPZ
廠商: Analog Devices Inc
文件頁數(shù): 4/76頁
文件大小: 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產品變化通告: AD9549A Mask Change 22/Oct/2010
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網,SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
產品目錄頁面: 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 12 of 76
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
60
I
3.3 V CMOS
IO_UPDATE
I/O Update. A logic transition from 0 to 1 on this pin transfers data from the I/O
port registers to the control registers (see the Write section). This pin has an
internal 50 k pull-down resistor.
61
I
3.3 V CMOS
CSB
Chip Select. Active low. When programming a device, this pin must be held
low. In systems where more than one AD9549 is present, this pin enables
individual programming of each AD9549. This pin has an internal 100 k pull-
up resistor.
62
O
3.3 V CMOS
SDO
Serial Data Output. When the device is in 3-wire mode, data is read on this pin.
There is no internal pull-up/pull-down resistor on this pin.
63
I/O
3.3 V CMOS
SDIO
Serial Data Input/Output. When the device is in 3-wire mode, data is written
via this pin. In 2-wire mode, data reads and writes both occur on this pin. There
is no internal pull-up/pull-down resistor on this pin.
64
I
3.3 V CMOS
SCLK
Serial Programming Clock. Data clock for serial programming. This pin has an
internal 50 k pull-down resistor.
Exposed
Die Pad
O
GND
EPAD
Analog Ground. The exposed thermal pad on the bottom of the package pro-
vides the analog ground for the part. This exposed pad must be connected to
ground for proper operation.
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