參數(shù)資料
型號: AD9549ABCPZ
廠商: Analog Devices Inc
文件頁數(shù): 48/76頁
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 52 of 76
Addr
(Hex)
Type1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Bit 0
Default
(Hex)
Calibration (user-accessible trim)
0x0400
K-divider
K-divider, Bits[15:0]
0x01
0x0401
0x00
0x0402
M
CPFD gain
CPFD gain scale, Bits[2:0]
0x00
0x0403
M
CPFD gain, Bits[5:0]
0x20
0x0404
FPFD gain
FPFD gain, Bits[7:0]
0xC8
0x0405
Reserved
0x0406
RO
Part
version
Part
version
Part
version
Reserved
0x00 or
0x40
0x0407
Reserved
0x0408
0x0409
M
PFD offset
DPLL phase offset, Bits[7:0]
0x00
0x040A
M
DPLL phase offset, Bits[13:8]
0x00
0x040B
DAC
full-scale
current
DAC full-scale current, Bits[7:0]
0xFF
0x040C
DAC full-scale current,
Bits[9:8]
0x01
0x040D
Reserved
0x040E
Reserved
0x10
0x040F
Reference
bias level
DC input level, Bits[1:0]
0x00
0x0410
Reserved
Harmonic spur reduction
0x0500
M
Spur A
HSR-A
enable
Amplitude
gain × 2
Reserved
Spur A harmonic, Bits[3:0]
0x00
0x0501
M
Spur A magnitude, Bits[7:0]
0x00
0x0502
M
0x00
0x0503
M
Spur A phase, Bits[7:0]
0x00
0x0504
M
Spur A
phase,
Bit 8
0x00
0x0505
M
Spur B
HSR-B
enable
Amplitude
gain × 2
Reserved
Spur B harmonic[3:0]
0x00
0x0506
M
Spur B magnitude, Bits[7:0]
0x00
0x0507
M
0x00
0x0508
M
Spur B phase, Bits[7:0]
0x00
0x0509
M
Spur B
phase,
Bit 8
0x00
1 Types of registers: RO = read-only, AC = autoclear, M = mirrored (also called buffered). A mirrored register needs an I/O update for the new value to take effect.
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