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參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 37 of 76
Single-Ended CMOS Output
In addition to the high speed differential output clock driver, the
AD9549 provides an independent, single-ended output, CMOS
clock driver. It serves as a relatively low speed (<150 MHz) clock
source. The origin of the signal generated by the CMOS clock
driver is determined by the appropriate control bits in the I/O
register map. The user can select one of two sources under
program control.
One source is the signal generated by the DDS after it has been
externally filtered and brought back on chip. In this configura-
tion, the CMOS clock driver generates the same frequency as
appears at the output of the DDS.
Note that in this configuration, the DDS output frequency must
not exceed 50 MHz.
The other source is the output of the feedback divider (S-divider).
In this configuration, the CMOS clock driver generates the same
frequency as the input reference after optional prescaling by the
R-divider (that is, fCMOS = fR/R), which is inherently limited to
a maximum of 25 MHz.
FREQUENCY SLEW LIMITER
The frequency slew limiting capability enables users to specify the
maximum rate of frequency change that appears at the output.
The function is programmable via the I/O register map. Program
control a bit to enable/disable the function (the default condition
is disable) and a register that sets the desired slew rate.
The frequency slew limiter is located between the digital loop
filter and the CCI filter, as shown in Figure 47.
The frequency slew limiter sets a boundary on the rate of change of
the output frequency of the DDS. The frequency slew limiting
constant, KSLEW, is a 48-bit value stored in the I/O register map.
The value of the constant is determined by
δt
δf
f
K
S
P
SLEW
IO
2
48
2
round
where:
PIO
is the value stored in the I/O register map for the P-divider.
fS
is the DAC sample rate.
δf/δt
is the desired frequency slew rate limitation.
For example, if fS = 1 GHz, PIO = 9, and δf/δt = 5 kHz/sec, then
3
2
9
48
10
5
(
)
10
(
2
round
SLEW
K
= 721
The resulting slew rate can be calculated as
IO
P
S
SLEW
f
K
δt
δf
48
2
The preceding example yields δf/δt = 5.003 kHz/sec.
FREQUENCY ESTIMATOR
The frequency estimation function automatically sets the DDS
output frequency so that the feedback frequency (fDDS/S) and the
prescaled reference frequency (fREF_IN/R) are matched within an
error tolerance (ε0). Its primary purpose is to allow the PLL to
quickly lock when the reference frequency is not known. The error
tolerance is defined as a fractional error and is controlled by
a 16-bit programmable value (K) via the I/O register map.
The precision of any frequency measurement is dependent on
the following two factors:
The timing resolution of the measurement device (δt)
The duration of the measurement (Tmeas)
The frequency estimator uses fS as its measurement reference, so
δt = 1/fS (that is, δt = 1 ns for a 1 GHz DAC sample rate). The
duration of the measurement is controlled by K, which establishes
a measurement interval that is K cycles of the measured signal
such that Tmeas = KR/fREF_IN.
The frequency estimator uses a 17-bit counter to accumulate the
number of δt periods within the measurement interval. The finite
capacity of the counter puts an upper limit on the duration of the
measurement, which is constrained to Tmax = 217/fS. If fS = 1 GHz,
this equates to ~131 μs. The fact that the measurement time is
bounded by Tmax means there is a limit to the largest value of K
(KMAX) that can be used without causing the counter to overflow.
The value of KMAX is given by
KMAX = floor
ρ
535
,
65
where:
R
S
f
R
f
ρ
R is the modulus of the feedforward divider.
fR is the input reference frequency.
0
67
44-
04
7
1
0
FREQUENCY
SLEW LIMIT
ENABLE
FREQUENCY
SLEW
LIMITER
δf/δt
SLEW
LIMIT
VALUE
DIGITAL
LOOP
FILTER
CCI
FILTER
TO
DDS
÷P
SYSCLK
TIME
TO
DIGITAL
CONVERTER
(PHASE
DETECTOR)
FROM “S”-DIVIDER
REF IN
÷R
Figure 47. Frequency Slew Limiter
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參數(shù)描述 |
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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