參數(shù)資料
型號(hào)： AD9549ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/76頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 34 of 76
The SYSCLK PLL multiplier path is enabled by a Logic 0
(default) in the PD SYSCLK PLL bit of the I/O register map.
The SYSCLK PLL multiplier can be driven from the SYSCLK
input pins by one of two means depending on the logic level
applied to the 1.8V CMOS CLKMODESEL pin. When
CLKMODESEL = 0, a crystal can be connected directly across
the SYSCLK pins. When CLKMODESEL = 1, the maintaining
amp is disabled, and an external frequency source (oscillator,
signal generator, etc.) can be connected directly to the SYSCLK
input pins. Note that CLKMODESEL = 1 does not disable the
system clock PLL.
The maintaining amp on the AD9549 SYSCLK pins is intended for
25 MHz, 3.2 mm × 2.5 mm AT cut fundamental mode crystals
with a maximum motional resistance of 100 Ω. The following
crystals, listed in alphabetical order, meet these criteria (as of
the revision date of this data sheet):
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
Fox FX3225BS
NDK NX3225SA
Note that while these crystals meet the preceding criteria
according to their data sheets, Analog Devices, Inc., does not
guarantee their operation with the AD9549, nor does Analog
Devices endorse one supplier of crystals over another.
When the SYSCLK PLL multiplier path is disabled, the AD9549
must be driven by a high frequency signal source (500 MHz to
1 GHz). The signal thus applied to the SYSCLK input pins
becomes the internal DAC sampling clock (fS) after passing
through an internal buffer.
SYSCLK PLL Doubler
The SYSCLK PLL multiplier path offers an optional SYSCLK
PLL doubler. This block comes before the SYSCLK PLL
multiplier and acts as a frequency doubler by generating a pulse
on each edge of the SYSCLK input signal. The SYSCLK PLL
multiplier locks to the falling edges of this regenerated signal.
The impetus for doubling the frequency at the input of the
SYSCLK PLL multiplier is that an improvement in overall phase
noise performance can be realized. The main drawback is that
the doubler output is not a rectangular pulse with a constant
duty cycle even for a perfectly symmetric SYSCLK input signal.
This results in a subharmonic appearing at the same frequency
as the SYSCLK input signal, and the magnitude of the subhar-
monic can be quite large. When employing the doubler, care
must be taken to ensure that the loop bandwidth of the SYSCLK
PLL multiplier adequately suppresses the subharmonic.
The benefit offered by the doubler depends on the magnitude
of the subharmonic, the loop bandwidth of the SYSCLK PLL
multiplier, and the overall phase noise requirements of the
specific application. In many applications, the AD9549 clock
output is applied to the input of another PLL, and the
subharmonic is often suppressed by the relatively narrow
bandwidth of the downstream PLL.
Note that generally, the benefits of the SYSCLK PLL doubler are
realized for SYSCLK input frequencies of 25 MHz and above.
SYSCLK PLL Multiplier
When the SYSCLK PLL multiplier path is employed, the
frequency applied to the SYSCLK input pins must be limited so
as not to exceed the maximum input frequency of the SYSCLK
PLL phase detector. A block diagram of the SYSCLK generator
is shown in Figure 43.
06744-
043
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
VCO
÷2
÷N
~2pF
(N = 2 TO 33)
KVCO
(HI/LO)
2
ICP
(125A, 250A, 375A)
SYSCLK PLL MULTIPLIER
LOOP_FILTER
FROM
SYSCLK
INPUT
DAC
SAMPLE
CLOCK
1GHz
Figure 43. Block Diagram of the SYSCLK PLL
The SYSCLK PLL multiplier has a 1 GHz VCO at its core. A phase/
frequency detector (PFD) and charge pump provide the steering
signal to the VCO in typical PLL fashion. The PFD operates on
the falling edge transitions of the input signal, which means that
the loop locks on the negative edges of the reference signal. The
charge pump gain is controlled via the I/O register map by selecting
one of three possible constant current sources ranging from 125 μA
to 375 μA in 125 μA steps. The center frequency of the VCO is
also adjustable via the I/O register map and provides high/low
gain selection. The feedback path from VCO to PFD consists of
a fixed divide-by-2 prescaler followed by a programmable divide-
by-N block, where 2 ≤ N ≤ 33. This limits the overall divider
range to any even integer from 4 to 66, inclusive. The value of
N is programmed via the I/O register map via a 5-bit word that
spans a range of 0 to 31, but the internal logic automatically adds
a bias of 2 to the value entered, extending the range to 33. Care
should be taken when choosing these values so as to not exceed
the maximum input frequency of the SYSCLK PLL phase detector
or SYSCLK PLL doubler. These values can be found in the AC
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