- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9674 > AD9549ABCPZ (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當(dāng)前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD9549
Rev. D | Page 61 of 76
FREE-RUN (SINGLE-TONE) MODE (REGISTER 0x01A0 TO REGISTER 0x01AD)
Register 0x01A0 to Register 0x01A5—Reserved
Register 0x01A6—FTW0 (Frequency Tuning Word)
Table 60.
Bit
Bit Name
Description
[7:0]
FTW0
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
Table 61.
Bit
Bit Name
Description
[15:8]
FTW0
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
Table 62.
Bit
Bit Name
Description
[23:16]
FTW0
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
Table 63.
Bit
Bit Name
Description
[31:24]
FTW0
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
Table 64.
Bit
Bit Name
Description
[39:32]
FTW0
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
Table 65.
Bit
Bit Name
Description
[47:40]
FTW0
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN2814ACPZ | IC CLOCK/DATA RECOVERY 32LFCSP |
| SM802105UMG | IC SYNTHESIZER 2CH 24-QFN |
| SM802104UMG | IC SYNTHESIZER 2CH 24-QFN |
| SM843001-212KA | IC CLK SYNTHESIZER FIBRE 8-TSSOP |
| MS27466T25F4S | CONN RCPT 56POS WALL MT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。