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參數(shù)資料
型號： AD9549ABCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 23/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 3 of 76
REVISION HISTORY
1
2/10—Rev. C to Rev. D
Changes to IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30,
Pin44, Pin 45) Parameter .................................................................4
Changes to Total Power Dissipation Parameter and Added
Endnote 4 ...........................................................................................5
Changes to Pin 59 Description......................................................11
Changes to Direct Digital Synthesizer (DDS) Section ...............20
Changes to Power-Up Section .......................................................42
Changes to Address 0x0002 Default Value (in Table 13) ...........48
Changes to Address 0x0400 and Address 0x40E Default Values
(in Table 13) .....................................................................................52
5/10—Rev. B to Rev. C
Deleted 64-Lead LFCSP (CP-64-1).................................. Universal
Changes to SYSCLK PLL Enabled/Minimum Differential Input
Level Parameter, Table 2 ...................................................................6
Updated Outline Dimensions........................................................74
Changes to Ordering Guide...........................................................74
1/10—Rev. A to Rev. B
Changes to I/O Register Map Section, Introduction and
Table 13.............................................................................................48
Changes to Register 0x0405 to Register 0x0408—Reserved
Section ..............................................................................................70
Added Register 0x0406—Part Version Section...........................71
12/09—Rev. 0 to Rev. A
Added 64-Lead LFCSP (CP-64-7) ................................... Universal
Changes to Total Power Dissipation Parameter............................5
Changes to Serial Port Timing Specifications and
Propagation Delay Parameters ........................................................8
Added Exposed Paddle Notation to Figure 2; Changes to
Table 4...............................................................................................10
Corrected DDS Phase Offset Resolution from 16 Bits to
14 Bits Throughout; Change to Figure 25....................................20
Changes to Phase Lock Detection Section ..................................24
Change to Figure 30........................................................................25
Changes to Loss of Reference and Reference Frequency
Monitor Sections .............................................................................26
Change to Output Frequency Range Control Section ...............32
Change to Figure 46........................................................................36
Changes to Frequency Estimator Section ....................................37
Changes to Programming Sequence Section ..............................42
Changes to Power Supply Partitioning Section...........................43
Change to Serial Control Port Section .........................................44
Changes to Figure 54 ......................................................................46
Added Exposed Paddle Notation to Outline Dimensions and
Changes to Ordering Guide...........................................................74
8/07—Revision 0: Initial Version
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9549ABCPZ-REEL7 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
AD9549APCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer
AD9549BCPZ 制造商:Analog Devices 功能描述:
AD9549BCPZ-REEL7 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel
AD9549BCPZ-TR 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel
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