參數(shù)資料
型號： AD9549ABCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 75/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
AD9549
Rev. D | Page 8 of 76
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOCK DETECTION
Phase Lock Detector
Time Threshold Programming Range
0
2097
μs
FPFD_gain = 200
Time Threshold Resolution
0.488
ps
FPFD_gain = 200
Lock Time Programming Range
32 × 109
275
sec
In power-of-2 steps
Unlock Time Programming Range
192 ×
109
67 × 103
sec
In power-of-2 steps
Frequency Lock Detector
Normalized Frequency Threshold
Programming Range
0
0.0021
FPFD_gain = 200; normalized to (fREF/R)2; see the
Normalized Frequency Threshold
Programming Resolution
5 ×
1013
FPFD_gain = 200; normalized to (fREF/R)2; see the
Frequency Lock Detection section for details
Lock Time Programming Range
32 × 109
275
sec
In power-of-2 steps
Unlock Time Programming Range
192 ×
109
67 × 103
sec
In power-of-2 steps
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
15
s
Time Required to Leave Power-Down
18
s
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
60
ns
Time from rising edge of RESET to high-Z on the S1,
S2, S3, and S4 configuration pins
Reset Deassert to Low-Z Time
for S1 to S4 Configuration Pins
30
ns
Time from falling edge of RESET to low-Z on the S1, S2,
S3, and S4 configuration pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/tCLK )
25
50
MHz
Refer to
Figure 58 for all write-related serial port
parameters, maximum SCLK rate for readback is
governed by tDV
SCLK Pulse Width High, tHIGH
8
ns
SCLK Pulse Width Low, tLOW
8
ns
SDO/SDIO to SCLK Setup Time, tDS
1.93
ns
SDO/SDIO to SCLK Hold Time, tDH
1.9
ns
SCLK Falling Edge to Valid Data on
SDIO/SDO, tDV
11
ns
Refer to
CSB to SCLK Setup Time, tS
1.34
ns
CSB to SCLK Hold Time, tH
0.4
ns
CSB Minimum Pulse Width High, tPWH
3
ns
IO_UPDATE Pin Setup Time
from SCLK Rising Edge of the Final Bit
tCLK
sec
tCLK = period of SCLK in Hz
IO_UPDATE Pin Hold Time
tCLK
sec
tCLK = period of SCLK in Hz
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver
2.8
ns
FDBK_IN to HSTL Output Driver with 2×
Frequency Multiplier Enabled
7.3
ns
FDBK_IN to CMOS Output Driver
8.0
ns
FDBK_IN Through S-Divider to CMOS
Output Driver
8.6
ns
Frequency Tuning Word Update,
IO_UPDATE Pin Rising Edge to DAC
Output
60/fs
ns
fs = system clock frequency in GHz
相關(guān)PDF資料
PDF描述
ADN2814ACPZ IC CLOCK/DATA RECOVERY 32LFCSP
SM802105UMG IC SYNTHESIZER 2CH 24-QFN
SM802104UMG IC SYNTHESIZER 2CH 24-QFN
SM843001-212KA IC CLK SYNTHESIZER FIBRE 8-TSSOP
MS27466T25F4S CONN RCPT 56POS WALL MT W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9549ABCPZ-REEL7 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
AD9549APCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer
AD9549BCPZ 制造商:Analog Devices 功能描述:
AD9549BCPZ-REEL7 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel
AD9549BCPZ-TR 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*