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參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 36 of 76
06744-
046
0
1
0
14
19
Q
D
48
14
DAC
(14-BIT)
I-SET
DDS+
DDS–
4
9
4
9
8
SHIFT
1
0
SHIFT
HEADROOM
CORRECTION
HARMONIC SPUR CANCELLATION
CH1 HARMONIC NUMBER
CH1 CANCELLATION PHASE OFFSET
CH2 HARMONIC NUMBER
CH2 CANCELLATION PHASE OFFSET
CH1 CANCELLATION MAGNITUDE
CH2 CANCELLATION MAGNITUDE
CH1 GAIN
CH2 GAIN
SPUR
CANCELLATION
ENABLE
ANGLE TO
AMPLITUDE
CONVERSION
DDS
PHASE
OFFSET
14
48
48-BIT ACCUMULATOR
DDS
48-BIT
FREQUENCY
TURNING WORD
(FTW)
SYSCLK
2-CHANNEL
HARMONIC
FREQUENCY
GENERATOR
CH1
CH2
Figure 46. Spur Reduction Technique
The mechanics of performing harmonic spur reduction are shown
in Figure 46. It essentially consists of two additional DDS cores
operating in parallel with the original DDS. This enables the user
to reduce two different harmonic spurs from the second to the
15th with nine bits of phase offset control (±π) and eight bits of
ampli-tude control.
The dynamic range of the cancellation signal is further aug-
mented by a gain bit associated with each channel. When this
bit is set, the magnitude of the cancellation signal is doubled by
employing a 1-bit left-shift of the data. However, the shift
operation reduces the granularity of the cancellation signal
magnitude.
Note that the full-scale amplitude of a cancellation spur is
approximately 60 dBc when the gain bit is a Logic 0 and
approximately 54 dBc when the gain bit is a Logic 1.
OUTPUT CLOCK DRIVERS AND 2× FREQUENCY
MULTIPLIER
There are two output drivers provided by the AD9549. The
primary supports differential 1.8 V HSTL output levels while
the secondary supports either 1.8 V or 3.3 V CMOS levels,
depending on whether Pin 37 is driven at 1.8 V or 3.3 V.
The primary differential driver nominally provides an output
voltage with 100 Ω load applied differentially (VDD VSS =
1.8 V). The source impedance of the driver is approximately
100 Ω for most of the output clock period; during transition
between levels, the source impedance reaches a maximum of
about 500 Ω. The driver is designed to support output
frequencies of up to and beyond the OC-12 network rate of
622.08 MHz.
The output clock can also be powered down by a control bit in
the I/O register map.
Primary 1.8 V Differential HSTL Driver
The DDS produces a sinusoidal clock signal that is sampled at
the system clock rate. This DDS output signal is routed off chip,
where it is passed through an analog filter and brought back on
chip for buffering and, if necessary, frequency doubling. Where
possible, for the best jitter performance, it is recommended that
the upconverter be bypassed.
The 1.8 V HSTL output driver should be ac-coupled, with
100 Ω termination at the destination. The driver design has low
jitter injection for frequencies in the range of 50 MHz to 750 MHz.
Refer to the AC Specifications section for the exact frequency
limits.
2× Frequency Multiplier
The AD9549 can be configured via the I/O register map with an
internal 2× delay-locked loop (DLL) multiplier at the input of
the primary clock driver. The extra octave of frequency gain
allows the AD9549 to provide output clock frequencies that
exceed the range available from the DDS alone. These settings
are found in Register 0x0010 and Register 0x0200.
The input to the DLL consists of the filtered DDS output signal
after it has been squared up by an integrated clock receiver circuit.
The DLL can accept input frequencies in the range of 200 MHz
to 400 MHz.
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相關代理商/技術參數(shù) |
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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