參數(shù)資料
型號(hào)： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁(yè)數(shù)： 101/168頁(yè)
文件大小： 943K
代理商： AM79C970
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AMD
P R E L I M I N A R Y
1-968
Am79C970
Initialization Block and Transmit
and Receive descriptor bit maps
are affected. When cleared, this
bit indicates that the PCnet-PCI
controller utilizes Am79C960
(PCnet-ISA) software structures.
Note:
Regardless of the setting
of SSIZE32, the Initialization
Block must always begin on a
double-word boundary.
The value of SSIZE32 is deter-
mined by the PCnet-PCI control-
ler. SSIZE32 is read only by the
host.
The PCnet-PCI controller uses
the setting of the Software Style
register (BCR20, bits 7-0/CSR58
bits 7-0) to determine the value
for this bit. SSIZE32 is cleared by
H_RESET and is not affected by
S_RESET or STOP.
If SSIZE32 is reset, then bits
IADR[31–24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32 bit address
bus during master accesses initi-
ated by the PCnet-PCI controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32=0 setting
will yield only 24 bits of address
for PCnet-PCI controller bus
master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the PCnet-PCI controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the PCnet-PCI
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit.
Software Style register. The
value in this register determines
the style of I/O and memory re-
sources that are used by the
PCnet-PCI controller. The Soft-
ware Style selection will affect
the interpretation of a few bits
within the CSR space and the
7–0 SWSTYLE
SWSTYLE
[7:0]
Style
Name
CSR-
PCNET SSIZE32 Interpretations
Altered Bit
00h
LANCE/
PCnet-
ISA
1
0
ALL CSR4 bits will
function as defined in the
CSR4 section.
TMD1[29] functions as
ADD_FCS
01h
ILACC
0
1
CSR4[9:8], CSR4[5:4]
and CSR4[1:0] will have
no function, but will be
writeable and readable.
CSR4[15:10], CSR4[7:6]
and CSR4[3:2] will
function as defined in the
CSR4 section.
TMD1[29] becomes
NO_FCS.
02h
PCnet-
PCI
1
1
ALL CSR4 bits will
function as defined in the
CSR4 section.
TMD1[29] functions as
ADD_FCS
All other
combs.
Res.
Undef.
Undef.
Undef.
width of the descriptors and
initialization block. Specifically:
All PCnet-PCI controller CSR
bits and BCR bits and all descrip-
tor, buffer and initialization block
entries not cited in the table
above are unaffected by the Soft-
ware Style selection and are
therefore always fully functional
as specified in the CSR and BCR
sections.
Read/write accessible only when
STOP bit is set.
The SWSTLYE register will con-
tain the value 00h following
H_RESET or S_RESET and will
be unaffected by STOP.
CSR59: IR Register
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. After H_RE-
SET, the value in this register will
be 0105h. The settings of this
register will have no effect on any
PCnet-PCI controller function.
This register always contains the
same value. It is not writeable.
Read accessible only when
STOP bit is set.
15–0
IRREG
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