參數(shù)資料
型號(hào)： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù)： 95/168頁
文件大小： 943K
代理商： AM79C970
AMD
P R E L I M I N A R Y
1-962
Am79C970
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO– yield “zero”
differential to operate trans-
former coupled loads (Ethernet 2
and 802.3). When TSEL = 1, the
DO+ idles at a higher value with
respect to DO– , yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the AUI network interface is
selected.
Read/write accessible only when
STOP bit is set. Cleared by
H_RESET or S_RESET.
Port Select bits allow for software
controlled selection of the net-
work medium.
PORTSEL settings of AUI and
10BASE-T are ignored when the
ASEL bit of BCR2 (bit 1) has
been set to ONE.
The network port configurations
are as follows:
8–7 PORTSEL[1:0]
Link
Status
PORTSEL
CSR15[1:0]
0 X
0 X
0 0
0 1
1 0
1 1
ASEL
(BCR2 [1])
1
1
0
0
X
X
Network
Port
AUI
10BASE-T
AUI
10BASE-T
Reserved
Reserved
(of 10BASE-T)
Fail
Pass
X
X
X
X
Read/write accessible only when
STOP bit is set. Cleared by
H_RESET or S_RESET and is
unaffected by STOP.
Internal Loopback. See the de-
scription of LOOP, CSR15[2].
Read/write accessible only when
STOP bit is set.
Disable Retry. When DRTY = “1”,
PCnet-PCI controller will attempt
only one transmission. If DRTY =
“0”, PCnet-PCI controller will at-
tempt 16 transmissions before
signaling a retry error.
Read/write accessible only when
STOP bit is set.
Force Collision. This bit allows
the collision logic to be tested.
PCnet-PCI controller must be in
internal loopback for FCOLL to
be valid. If FCOLL = “1”, a colli-
sion will be forced during loop-
back transmission attempts; a
6
INTL
5
DRTY
4
FCOLL
Retry Error will ultimately result.
If FCOLL = “0”, the Force Colli-
sion logic will be disabled.
FCOLL is defined after the In-
itialization Block is read.
Read/write accessible only when
STOP bit is set.
Disable Transmit CRC (FCS).
When DXMTFCS = 0, the trans-
mitter will generate and append a
FCS to the transmitted frame.
When DXMTFCS = 1, the FCS
logic is allocated to the receiver
and no FCS is generated or sent
with the transmitted frame.
DXMTFCS is overridden when
ADD_FCS is set in TMD1.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set and
ADD_FCS is clear for a particular
frame, no FCS will be generated.
The value of ADD_FCS is valid
only when STP is set in TMD1. If
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry.
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write accessible only when
STOP bit is set.
Loopback
Enable
PCnet-PCI controller to operate
in full duplex mode for test pur-
poses. When LOOP = “1”, loop-
back is enabled. In combination
with INTL and MENDECL, vari-
ous loopback modes are defined
as follows:
3
DXMTFCS
2
LOOP
allows
LOOP
0
1
1
INTL
X
0
1
MENDECL
X
X
0
Loopback Mode
Non-loopback
External Loopback
Internal Loopback
Include MENDEC
Internal Loopback
Exclude MENDEC
1
1
1
Read/write accessible only when
STOP bit is set. LOOP is cleared
by H_RESET or S_RESET and is
unaffected by STOP.
Disable Transmit results in
PCnet-PCI controller not access-
ing the Transmit Descriptor Ring
1
DTX
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