參數(shù)資料
型號(hào)： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁(yè)數(shù)： 110/168頁(yè)
文件大小： 943K
代理商： AM79C970
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P R E L I M I N A R Y
AMD
1-977
Am79C970
BCR0: Master Mode Read Active
Bit
Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. After H_RE-
SET, the value in this register will
be 0005h. The settings of this
register will have no effect on any
PCnet-PCI controller function.
Writes to this register have no ef-
fect on the operation of the
PCnet-PCI controller and will not
alter the value that is read.
15–0 MSRDA
BCR1: Master Mode Write Active
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. After H_RE-
SET, the value in this register will
be 0005h. The settings of this
register will have no effect on any
PCnet-PCI controller function.
Writes to this register have no ef-
fect on the operation of the
PCnet-PCI controller and will not
alter the value that is read.
15–0 MSWRA
BCR2: Miscellaneous Configuration
Bit
Name
Description
Note that all bits in this register
are programmable through the
EEPROM PREAD operation.
Reserved locations. Written as
ZEROs and read as undefined.
Reserved location. Written and
read as ZERO.
When set, this bit allows external
loopback packets to pass onto
the network through the TMAU
interface, if the TMAU interface
has been selected. If the TMAU
interface has not been selected,
then this bit has no effect.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
Reserved locations. Written and
read as ZERO.
IEEE Shadow Ram Write En-
able. The PCnet-PCI controller
contains a shadow RAM on
board for storage of the IEEE ad-
dress
following
31–16 RES
15
RES
14
TMAULOOP
13–9
RES
8
IESRWE
the
serial
EEPROM read operation. Ac-
cesses to APROM I/O Re-
sources will be directed toward
this RAM. When IESRWE is set
to a ONE, then write access to
the shadow RAM will be enabled.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
Reserved location. The default of
this bit is zero. Writing a ONE to
this bit has no effect on the op-
eration
of
the
controller.
This reserved location is cleared
by H_RESET and is unaffected
by S_RESET or STOP.
Reserved locations. Written and
read as ZERO.
This bit selects one of two differ-
ent sleep modes.
If AWAKE=1 and the
SLEEP
pin
is asserted, the PCnet-PCI con-
troller goes into snooze mode. If
AWAKE=0 and the
SLEEP
pin is
asserted, the PCnet-PCI control-
ler goes into coma mode. See
Power Saving Modes section for
more details.
This bit only has meaning when
the 10BASE-T network interface
is selected.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
Auto Select. When set, the
PCnet-PCI controller will auto-
matically select the operating
media interface port. If ASEL has
been set to a ONE, then when the
10BASE-T transceiver is in the
link pass state (due to receiving
valid frame data and/or Link Test
pulses or the DLNKTST bit is
set), the 10BASE-T port will be
used. If ASEL has been set to a
ONE, then when the 10BASE-T
port is in the link fail state, the AUI
port will be used. Switching be-
tween the ports will not occur dur-
ing transmission, to avoid any
type of fragment generation.
When ASEL is set to ONE, Link
Beat Pulses will be transmitted
on the 10BASE-T port, regard-
less of the state of Link Status.
When ASEL is reset to ZERO,
Link Beat Pulses will only be
transmitted on the 10BASE-T
7
RES
PCnet-PCI
6–3
RES
2
AWAKE
1
ASEL
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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