- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C970 (Advanced Micro Devices, Inc.) PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C970 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線 |
| 文件頁(yè)數(shù)： | 161/168頁(yè) |
| 文件大?。?/td> | 943K |
| 代理商： | AM79C970 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)當(dāng)前第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)
AMD
1-1028
Am79C970
Note that the PCnet-PCI controller might write a ZERO
to ENP location in the 3rd descriptor. Here are the two
possibilities:
1. If the controller finishes the data transfers into
buffer number 2 after the driver writes the applica-
tions modified buffer pointer into the third descrip-
tor, then the controller will write a ZERO to ENP for
this buffer and will write a ZERO to OWN and STP.
2. If the controller finishes the data transfers into
buffer number 2 before the driver writes the appli-
cations modified buffer pointer into the third de-
scriptor, then the controller will complete the frame
in buffer number two and then skip the then un-
owned third buffer. In this case, the PCnet-PCI
controller will not have had the opportunity to RE-
SET the ENP bit in this descriptor, and it is possi-
ble that the software left this bit as ENP=1 from the
last time through the ring. Therefore, the software
must treat the location as a don’t care; The rule is,
after finding ENP=1 (or ERR=1) in descriptor num-
ber 2, the software must ignore ENP bits until it
finds the next STP=1.
Assume that instead of the expected 1060 byte
frame, a 100 byte frame arrives, because there
was an error in the network, or because this is the
last frame in a file transmission sequence, or per-
haps because it is an acknowledge frame.
* Same as note in case 2 above, except that in this case,
it is very unlikely that the driver can respond to the inter-
rupt and get the pointer from the application before the
PCnet-PCI controller has completed its poll of the next
descriptors. This means that for almost all occurrences
of this case, the PCnet-PCI controller will not find the
OWN bit set for this descriptor and therefore, the ENP
bit will almost always contain the old value, since the
PCnet-PCI controller will not have had an opportunity to
modify it.
** Note that even though the PCnet-PCI controller will
write a ZERO to this ENP location, the software should
treat the location as a don’t care, since after finding the
ENP=1 in descriptor number 2, the software should ig-
nore ENP bits until it finds the next STP=1.
OWN
1
1
0
1
1
0
1
STP
1
0
0
1
0
0
1
ENP
X
X
X
X
X
X
X
OWN
0
0
0
1
1
0
1
STP
1
0
0
1
0
0
1
ENP
=
1
0**
*
X
X
X
X
(after frame arrival)
bytes 1–100
discarded buffer
discarded buffer
controller’s current location
not yet used
not yet used
not yet used
1
2
3
4
5
6
etc.
Descriptor
Number
Before the Frame Arrives
After the Frame has Arrived
Comments
=
ENP or ERR
Buffer Size Tuning
For maximum performance, buffer sizes should be ad-
justed depending upon the expected frame size and the
values of the interrupt latency and application call la-
tency. The best driver code will minimize the CPU utili-
zation while also minimizing the latency from frame end
on the network to frame sent to application from driver
(frame latency). These objectives are aimed at increas-
ing throughput on the network while decreasing CPU
utilization.
Note that the buffer sizes in the ring may be altered at
any time that the CPU has ownership of the correspond-
ing descriptor. The best choice for buffer sizes will maxi-
mize the time that the driver is swapped out, while
minimizing the time from the last byte written by the
PCnet-PCI controller to the time that the data is passed
from the driver to the application. In the diagram, this
corresponds to maximizing S0, while minimizing the
time between C9 and S8. (The timeline happens to
show a minimal time from C9 to S8.)
Note that by increasing the size of buffer number 1, we
increase the value of S0. However, when we increase
the size of buffer number 1, we also increase the value
of S4. If the size of buffer number 1 is too large, then the
driver will not have enough time to perform tasks S2, S3,
S4, S5 and S6. The result is that there will be delay from
the execution of task C9 until the execution of task S8. A
perfectly timed system will have the values for S5 and
S7 at a minimum.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971 | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。