參數(shù)資料
型號(hào): AM79C970
廠商: Advanced Micro Devices, Inc.
英文描述: PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述: PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁(yè)數(shù): 127/168頁(yè)
文件大小: 943K
代理商: AM79C970
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AMD
P R E L I M I N A R Y
1-994
Am79C970
Transmit Descriptors
When SSIZE32=0 (BCR 20, bit 8), then the software
structures are defined to be 16 bits wide, and transmit
descriptors look like this (CXDA = Current Transmit De-
scriptor Address):
Table 17. 16-Bit Data Structure Transmit Descriptor
Address
CXDA+00h
CXDA+02h
15
14
13
12
11
TBADR[15:0]
ONE
10
9
8
7–0
OWN
ERR
ADD_/
NO_
FCS
1
EX
DEF
MORE
DEF
STP
ENP
TBADR[23:16]
CXDA+04h
CXDA+06h
1
1
1
BCNT
BUFF
UFLO
LCOL
LCAR
RTRY
TDR
When SSIZE32=1 (BCR 20, bit 8), then the software structures are defined to be 32 bits wide, and transmit descriptors
look like this (CXDA = Current Transmit Descriptor Address):
Table 18. 32-Bit Data Structure Transmit Descriptor
Address
CXDA+00h
CXDA+04h
31
30
29
28
27
26
TBADR[31:0]
DEF
25
24
23–16
15–4
3–0
OWN
ERR
ADD_/
NO_
FCS
EX
DEF
MORE
ONE
STP
ENP
RES
1111
BCNT
CXDA+08h
BUFF
UFLO
LCOL
LCAR
RTRY
TDR
RES
TRC
CXDA+0Ch
RESERVED
TMD0
Bit
Name
Description
31–0
TBADR
Transmit Buffer address. This
field contains the address of the
transmit buffer that is associated
with this descriptor.
TMD1
Bit
Name
Description
31
OWN
This bit indicates that the de-
scriptor entry is owned by the
host (OWN=0) or by the PCnet-
PCI controller (OWN=1). The
host sets the OWN bit after filling
the buffer pointed to by the de-
scriptor entry. The PCnet-PCI
controller clears the OWN bit af-
ter transmitting the contents of
the buffer. Both the PCnet-PCI
controller and the host must not
alter a descriptor entry after it has
relinquished ownership.
ERR is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is set by
30
ERR
the PCnet-PCI controller and
cleared by the host. This bit is set
in the current descriptor when the
error occurs, and therefore may
be set in any descriptor of a
chained buffer transmission.
Bit 29 functions as ADD_FCS
when programmed for the default
I/O style of PCnet-ISA and when
programmed for the I/O style
PCnet-PCI controller. Bit 29
functions as NO_FCS when
programmed for the I/O style
ILACC.
ADD_FCS dynamically controls
the generation of FCS on a frame
by frame basis. It is valid only if
the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS is ignored and trans-
mitter FCS generation is acti-
vated. When ADD_FCS = 0, FCS
generation is controlled by
DXMTFCS. ADD_FCS is set by
the host, and unchanged by the
PCnet-PCI controller. This was a
reserved bit in the LANCE
29
ADD_FCS_
NO_FCS
ADD_FCS
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